NAND Flash Multi-Plane Read Control for Asynchronous Access
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Solution Overview
Problem
Existing NAND Flash memory devices perform multi-plane read operations synchronously, limiting system performance as the host cannot issue read instructions when the memory device is busy, restricting operation speed and flexibility.
Innovation Solution
Implementing asynchronous multi-plane independent (AMPI) read operations using a main microcontroller unit (MCU) and multiple AMPI read units, along with a multiplexing circuit to manage AMPI and non-AMPI read control signals, allowing read instructions to be issued even when the memory device is busy, thereby improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous multi-plane read operations are used, then the memory device can maintain simple control logic, but the host cannot issue read instructions when the memory device is busy, limiting system performance
Solution Approach 1:
The control logic is segmented into a main MCU and multiple independent AMPI read units. Each AMPI read unit is dedicated to controlling read operations on a specific memory plane, allowing parallel and asynchronous operation. This segmentation enables the host to issue read instructions to different planes simultaneously without waiting for previous operations to complete, thereby improving system performance while maintaining manageable complexity through modular design.
Solution Approach 2:
A multiplexing circuit is introduced as an intermediary component to manage control signals between the main MCU, AMPI read units, and memory planes. The multiplexing circuit routes control signals appropriately based on the operation type (AMPI or non-AMPI), enabling flexible operation modes without requiring complex direct control logic in each component.
2Ease of operation
If asynchronous multi-plane independent read operations are implemented, then read instructions can be issued even when the memory device is busy, but the number of control units increases
Solution Approach 1:
The control functionality is divided into a main MCU for overall coordination and multiple specialized AMPI read units, each responsible for a specific memory plane. This segmentation allows the system to achieve high operation flexibility through asynchronous multi-plane reads while keeping each control unit's complexity low and manageable.
Solution Approach 2:
The main MCU is designed to handle both AMPI and non-AMPI read operations, providing multi-functionality. This universal control unit can dynamically switch between operation modes, reducing the need for entirely separate control paths and mitigating the increase in overall device complexity despite adding AMPI read units.
3Speed
If multiple AMPI read units are added to enable asynchronous reads, then operation speed increases, but power consumption increases
Solution Approach 1:
By segmenting the control logic into specialized AMPI read units, each unit can be optimized for low-power operation during async reads. The segmentation allows the system to activate only the necessary read units based on the specific operation being performed, rather than maintaining full power consumption across all control units continuously.
Solution Approach 2:
Each AMPI read unit is designed to autonomously manage its own operation and power state, enabling it to enter low-power modes when not actively performing read operations. This self-service capability allows the system to achieve high operation speed when needed while minimizing power consumption during idle or low-activity periods.
Data Source
AI summary
A memory device includes N memory planes (N is an integer greater than 1), M asynchronous multi-plane independent (AMPI) read units (M is an integer smaller than or equal to N), a first microcontroller unit (MCU), and a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units. Each AMPI read unit is configured to provide an AMPI read control signal for a respective memory plane to control an AMPI read operation on the respective memory plane. The first MCU is configured to provide a non-AMPI read control signal for each memory plane to control a non-AMPI read operation on each memory plane. The multiplexing circuit is configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of M AMPI read control signals to the respective memory plane from the corresponding AMPI read unit.