NAND Flash Discharge Circuit for Safe Post-Erase Voltage Control
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Solution Overview
Problem
The challenge in 3D NAND flash memory is the critical timing of discharge operations post-erase, which can lead to source/drain junction breakdown and FN stress in discharge transistors due to improper switching, affecting performance and reliability.
Innovation Solution
A discharge circuit with a MOSFET-based discharge transistor, a source line detect circuit, and a gate discharge circuit to maintain a constant voltage difference, ensuring precise timing and preventing junction breakdown and FN stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discharge transistor is used to discharge the source line and bit line after erase operation, then the electrical potentials can be discharged, but the timing of discharge operation is critical and can lead to source/drain junction breakdown and FN stress in the discharge transistor
Solution Approach 1:
The gate discharge circuit maintains a constant voltage difference between the gate terminal and source terminal of the discharge transistor before the discharge operation begins. This preliminary voltage setup ensures that when the discharge transistor switches on, the voltage difference across source and drain junctions is already controlled, preventing junction breakdown and FN stress during the actual discharge operation.
Solution Approach 2:
The gate discharge circuit acts as an intermediary mechanism that indirectly controls the voltage conditions during discharge. Instead of directly controlling the source-drain voltage, it maintains a constant gate-source voltage difference, which in turn regulates the voltage across source and drain junctions, preventing harmful voltage spikes while enabling discharge functionality.
2Loss of time
If the discharge transistor switches on too early or too late, then discharge timing control is needed, but improper timing causes source/drain junction breakdown
Solution Approach 1:
The constant voltage difference is established in the gate-source terminals before discharge begins, preparing the transistor in advance with controlled voltage conditions. This preliminary voltage setup ensures that regardless of when the discharge transistor switches on, the voltage difference across source and drain junctions remains controlled, preventing junction breakdown and FN stress.
Solution Approach 2:
The gate discharge circuit continuously maintains the constant voltage difference between gate and source terminals during the discharge operation. This active voltage regulation provides feedback control that ensures the voltage conditions remain within safe limits throughout the discharge process, preventing harmful effects even as voltages change dynamically.
Data Source
AI summary
A method of operating a memory device is disclosed. The memory device includes a memory string coupled with a bit line and a common source line. An erase voltage is applied to the bit line and the common source line in an erase operation. The bit line and the common source line are discharged in a discharge operation after the erase operation. A voltage difference between the bit line and the common source line is less than a first predetermined value during a period of the discharge operation.