Flash FPGA Configuration Circuit for Programming Interference Suppression
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Solution Overview
Problem
During the production of flash-type FPGAs, applying a high voltage for programming operations causes a drift in the threshold voltage of previously programmed flash switches, leading to increased signal transmission delay and a failure to meet timing requirements.
Innovation Solution
A configuration control circuit for flash-type FPGAs is introduced, incorporating a word line, bit line, and programming selection circuit to manage voltage paths during programming, ensuring that high voltages only affect the targeted flash memory cells and not others, using selection transistors and switch transistors to control voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a high voltage is applied to a flash switch to perform a programming operation, then the programming operation can be completed, but a previously programmed flash switch is affected causing a drift in threshold voltage and increasing signal transmission delay
Solution Approach 1:
The patent segments the bit line voltage application by introducing a programming selection circuit that selectively connects the programming BL voltage to specific flash memory cells based on row and column selection signals. This segmentation ensures that high programming voltage is applied only to targeted cells rather than all cells in a column, preventing interference with previously programmed cells and maintaining threshold voltage stability.
Solution Approach 2:
The patent implements local quality by making the bit line voltage application selective rather than uniform. The programming selection circuit applies different voltage states to different flash memory cells within the same column based on the programming operation requirements. This localized voltage control ensures that only the specific cell being programmed receives the high programming voltage, while other cells maintain their original voltage state, thereby preventing threshold voltage drift in previously programmed cells.
2Ease of manufacture
If a high voltage is applied to a flash switch to perform a programming operation, then the programming operation can be completed, but the signal transmission delay increases and timing requirements are not met
Solution Approach 1:
The patent segments the programming voltage application in both spatial and temporal dimensions. By using row selection and column selection signals to control the programming selection circuit, the high voltage is applied only to the specific flash memory cell that needs programming at a specific time. This segmented approach prevents cumulative delays that would occur if all cells were subjected to programming voltage simultaneously, thereby maintaining timing requirements.
Solution Approach 2:
The patent employs preliminary anti-action by using the programming selection circuit to prevent programming interference before it can affect previously programmed cells. The selection circuit proactively blocks the programming BL voltage from reaching unselected cells, thereby preventing the threshold voltage drift and signal transmission delay that would otherwise occur. This preventive measure ensures that timing requirements are maintained throughout the programming process.
3Ease of manufacture
If a programming BL voltage is provided through a BL channel to a flash memory cell, then the programming operation can be performed, but programming interference affects other flash memory cells in the same column
Solution Approach 1:
The patent introduces a programming selection circuit as an intermediary between the BL channel and the flash memory cells. This intermediary circuit selectively connects or disconnects the programming BL voltage to specific cells based on row and column selection signals. By acting as a mediator, the programming selection circuit ensures that the high programming voltage from the BL channel is delivered only to the intended target cell while blocking interference to other cells in the same column, thereby eliminating programming interference.
Solution Approach 2:
The patent segments the connection between the BL channel and flash memory cells by introducing controllable switching elements in the programming selection circuit. This segmentation allows independent control of voltage application to each cell or small group of cells, preventing the propagation of programming interference to adjacent cells. The segmented architecture ensures that programming operations are isolated to specific cells while maintaining the ability to program any cell in the array.
Data Source
AI summary
A configuration control circuit of a flash-type FPGA capable of suppressing programming interference is provided. The configuration control circuit adds a programming selection circuit compared with a conventional configuration control circuit. When a programming operation is performed on a flash memory cell located in a target row and a target column, the programming selection circuit controls a path between a programming bit line (BL) voltage and a BL voltage obtaining terminal of the flash memory cell located in the target row and the target column to be turned on, and a path between the programming BL voltage and a BL voltage obtaining terminal of a flash memory cell located in another row and the target column to be turned off.