Memory Input Amplifier Circuit for Jitter and Duty Cycle Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently amplifying and processing high-speed data signals due to asymmetry in rise and fall operations of differential amplifiers, leading to jitter and duty cycle distortion, which affects interface speed and reliability.
Innovation Solution
Incorporating a source follower circuit in parallel with the differential amplifier to complement the response between rise and fall operations, stabilizing node voltages, and using specific transistor configurations to reduce jitter and pulse width variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a differential amplifier is used to amplify data signals, then signal amplification is achieved, but asymmetry in rise and fall operations causes jitter and duty cycle distortion
Solution Approach 1:
The amplifier is divided into two separate amplification paths: a differential amplifier for signal amplification and a source follower circuit for response time extension. This segmentation allows each circuit to be optimized for its specific function, resolving the contradiction between amplification accuracy and response symmetry.
Solution Approach 2:
The source follower circuit acts as an intermediary between the differential amplifier and the load, extending the response time to rise and fall operations. This intermediary component compensates for the asymmetry inherent in differential amplifiers, reducing jitter and duty cycle distortion while maintaining signal amplification accuracy.
2Speed
If interface speed is increased, then data processing capability is improved, but jitter and duty cycle distortion increase
Solution Approach 1:
The source follower circuit maintains continuous control over the response time to rise and fall operations, ensuring that even at high interface speeds, the amplification process remains symmetrical and jitter-free. This continuous adjustment of response timing allows high-speed operation without compromising signal integrity.
3Device complexity
If conventional amplifier circuits are used, then device complexity is reduced, but pulse width variations and jitter occur
Solution Approach 1:
The invention intentionally introduces asymmetry in the form of a unipolar source follower circuit to compensate for the inherent asymmetry in differential amplifier response. This deliberate asymmetric addition creates overall symmetry in the rise and fall operations, ensuring consistent pulse width and reduced jitter while maintaining relatively simple device structure.
Data Source
AI summary
An amplifier of an input circuit includes: a first PMOS transistor having a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second PMOS transistor having a gate connected to a fourth node that inputs a reference signal, a source connected to the second node, and a drain connected to a fifth node; a current source connected between a power supply voltage and the second node; a load circuit connected between the third node and a ground voltage; a first NMOS transistor having a gate connected to the first node, a drain connected to the power supply voltage, and a source connected to the fifth node; and a second NMOS transistor having a gate connected to the fourth node, a drain connected to the power supply voltage, and a source connected to the third node.