Staggered Triggering Control for Peak Current in Non-Volatile Memory
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Solution Overview
Problem
Non-volatile memory devices face challenges in handling peak current levels during simultaneous high voltage applications, leading to potential malfunctions and errors in programming, writing, and reading operations.
Innovation Solution
A staggered triggering method and control circuit are implemented, utilizing time delay circuits to manage peak current by sequentially activating high-voltage switches and sensing circuits, reducing the likelihood of excessive current flow and errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is applied simultaneously to a plurality of memory cells, then programming and writing operations can proceed in parallel improving speed, but excessive peak current flows causing voltage drops and potential device malfunction
Solution Approach 1:
The patent divides the simultaneous activation of all memory cells into segmented groups that are activated sequentially. The controller activates word lines in multiple stages, with each stage activating a subset of memory cells. This segmentation allows parallel operation within each stage while preventing excessive peak current by limiting the number of simultaneously active cells to a manageable level that the power supply can handle.
Solution Approach 2:
The patent implements periodic action by using multiple programming pulses applied in sequential stages rather than a single simultaneous pulse to all cells. Each pulse activates a specific group of memory cells for a predetermined time period, then deactivates before activating the next group. This periodic, staged approach maintains high overall productivity while controlling peak current within safe limits.
2Reliability
If high voltage is applied sequentially to each memory cell, then peak current is controlled within safe limits, but the operation time increases significantly reducing productivity
Solution Approach 1:
Instead of sequential activation of individual cells, the patent segments memory cells into multiple groups that are activated in parallel within each stage. This segmentation strategy maintains reliable current control by limiting simultaneous active cells while improving productivity by processing multiple cells concurrently in each stage, rather than one cell at a time.
Solution Approach 2:
The patent uses periodic action with multiple programming pulses applied in sequential stages. Each pulse activates a group of memory cells for a predetermined time, then deactivates before the next pulse. This periodic approach achieves both current control and acceptable operation time by balancing the number of simultaneously active cells across multiple timed stages.
3Productivity
If sensing circuits are operated simultaneously to detect data from multiple memory cells, then reading speed is improved, but excessive current flows increasing the probability of sensing errors
Solution Approach 1:
The patent segments the sensing operation into multiple stages, where sensing circuits detect data from different groups of memory cells sequentially rather than simultaneously. In each stage, a subset of sensing circuits is activated to read from a corresponding group of memory cells. This segmentation maintains high reading speed by processing multiple cells in parallel within each stage while preventing excessive peak current that would cause sensing errors.
Solution Approach 2:
The patent implements periodic sensing by applying multiple read pulses in sequential stages. Each pulse activates a specific group of sensing circuits for a predetermined time period to detect data from corresponding memory cells, then deactivates before activating the next group. This periodic, staged sensing approach achieves both fast reading and accurate measurement by controlling the number of simultaneously active sensing circuits.
4Loss of energy
If bit line detection circuits are driven one by one, then current consumption is reduced, but the detection time increases significantly
Solution Approach 1:
The patent segments bit line detection into multiple stages, where detection circuits process different groups of bit lines in parallel within each stage rather than sequentially one by one. This segmentation reduces total detection time by enabling concurrent processing of multiple bit lines while controlling current consumption by limiting the number of simultaneously active detection circuits to a level that manages peak current effectively.
Data Source
AI summary
A non-volatile memory device comprises an array of non-volatile memory cells, a controller in communication with the non-volatile memory cell, a row driver including a plurality of high-voltage switches for applying high-voltages to non-volatile memory cells, a column driver including a plurality of sensing circuits for monitoring the data of the non-volatile memory cells; and, a plurality of time delay circuits, wherein the time delay circuit is configured to reduce peak current caused by simultaneous application of high voltages to the non-volatile memory cells or simultaneous detection of current flowing across bit lines of the non-volatile memory cells.