Programmable Delay Circuit Using FeFET Memory States
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Solution Overview
Problem
Existing delay circuits require additional chip resources such as dedicated transistors, capacitors, and control signal routing for each selectable delay time, making them costly and inefficient in terms of on-chip resource utilization.
Innovation Solution
A programmable delay circuit utilizing state-programmable memory elements, such as ferroelectric field-effect transistors (FeFETs), which can be programmed to different polarization states to adjust delay times without the need for additional chip resources, by leveraging remanent polarization to shift threshold voltages in a non-volatile manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dedicated resources (transistors, capacitors, routing) are provided for each delay time, then delay adjustability is improved, but on-chip resource consumption increases
Solution Approach 1:
The patent implements a single delay circuit that can provide multiple different delay times by programming the state-programmable memory element with different polarization states. Instead of having separate dedicated delay circuits for each delay time, one universal delay circuit handles all delay requirements, thereby reducing on-chip resource consumption while maintaining full delay adjustability
Solution Approach 2:
The patent changes the threshold voltage parameter of the transistor by utilizing different remanent polarization states of the state-programmable memory element. By programming the memory element to different polarization states, the threshold voltage is adjusted, which in turn adjusts the delay time without requiring additional physical resources
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides adjustable delay times without the need for additional chip resources, enabling efficient integration into logic or analog circuits and allowing fine-tuning of delays through multiple stable states.
Implementation Method 1
leveraging remanent polarization to shift threshold voltages in a non-volatile manner
Data Source
AI summary
Disclosed herein is a programmable delay circuit for providing an adjustable delay for a signal transmitted from an input node to an output node. The adjustable delay circuit includes an input node; an output node; and a pair of inverter circuits coupled in series between the input node and the output node, wherein the pair of inverter circuits is configured to provide an adjustable delay for a signal transmitted from the input node to the output node. At least one inverter circuit of the pair of inverter circuits includes a state-programmable memory element that allows the pair of inverter circuits to be configurable between a first delay mode or a second delay mode.