Memory Sensing with Non-Regular Counter and Adaptive Reference Voltages

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Solution Overview

Problem

Conventional in-memory computing components face variability in the time required for internal circuitry to reach sufficient current or voltage values for value storage due to varying currents and voltages from bit lines, leading to inefficiencies and potential incorrect storage of counter values.

Innovation Solution

Implementing a circuit with a global programmable non-regular counter and dynamic reference voltages that adjust timing and voltage selection based on current levels, using a multiplexer to select appropriate reference voltages and current mirrors/capacitors to optimize the time for value storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a global regular counter and global fixed reference voltage are used, then the circuit structure is simple, but the timing for value storage varies greatly based on current and voltage levels

Engineering Contradiction:
Improvecircuit structureVSAvoidtiming variability
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements a non-regular counter that dynamically adjusts its counting behavior based on detected current levels. The counter modifies its counting rate or skips counts depending on the magnitude of the current, thereby adapting the timing of value storage to match the varying charge rates of the capacitor across different operating conditions. This dynamic adjustment eliminates timing variability while maintaining circuit simplicity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the counter based on the detected current level. By monitoring the current magnitude and adjusting the counter's behavior accordingly (e.g., changing counting intervals or rates), the system compensates for variations in capacitor charge rates, ensuring consistent timing for value storage without requiring a completely complex circuit redesign.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If individual local sensing circuits with separate counters are implemented, then timing accuracy for each circuit is improved, but the overall device complexity increases significantly

Engineering Contradiction:
Improvetiming accuracyVSAvoidnumber of sensing circuits
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent makes a single global non-regular counter serve multiple local sensing circuits simultaneously. The counter is shared across all sensing circuits, and its non-regular counting behavior is designed to accommodate the combined requirements of all circuits. This universal approach maintains timing accuracy for each circuit while avoiding the complexity of duplicating counters in every local sensing circuit.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges multiple counter functions into a single global non-regular counter that serves all local sensing circuits. By combining the counting functionality and making it shared rather than distributed, the system achieves the timing accuracy of individual counters while dramatically reducing the overall device complexity and component count.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If the counter counts at a fixed rate, then the counting operation is simple, but lower currents require more time to reach sufficient voltage values for storage

Engineering Contradiction:
Improvecounting speedVSAvoidvalue storage accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The non-regular counter dynamically adjusts its counting rate based on the detected current level. When lower currents are detected that would take longer to charge the capacitor to the reference voltage, the counter slows down its counting rate or inserts delay periods. This dynamic adjustment ensures that the counter only stores values when the capacitor has reached sufficient voltage, maintaining storage accuracy while adapting the counting speed to current conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback by monitoring the current level and using this information to control the counter's operation. The detected current magnitude feeds back to the counter logic, which then adjusts its counting behavior accordingly. This feedback mechanism ensures that the counter operates at appropriate speeds for each current level, maintaining both productivity and reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12354672B2Memory sensing with global non-regular counter and/or global multiple reference voltages
Publication Date: 2025.07.08 MACRONIX INTERNATIONAL CO LTD
  • US12354672B2 patent drawing
  • US12354672B2 patent drawing
  • US12354672B2 patent drawing

AI summary

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.