Serial Signal Processing Circuit With Clock-Phase Symbol Alignment
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Solution Overview
Problem
Existing signal processing circuits for serial communication standards like PCIe face challenges in efficient symbol alignment, often requiring large-scale multiplexers and data buffering, which lead to signal delays during symbol alignment.
Innovation Solution
A signal processing circuit that includes a shift register, a first flip-flop group, and a second circuit, where the second circuit adjusts the phase of the clock to ensure that the flip-flops fetch data starting with the bit data at the head of each symbol, eliminating the need for large-scale multiplexers and reducing data buffering, thereby minimizing signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large-scale multiplexers and data buffering are used for symbol alignment, then symbol alignment can be achieved, but signal delays increase and device complexity increases
Solution Approach 1:
The patent changes the parameter of clock phase by using a phase shift frequency divider to generate a parallel clock with adjusted phase relationship relative to the serial clock. This phase parameter adjustment enables the flip-flops to sample data at the correct timing without requiring large-scale multiplexers or extensive buffering, thus achieving symbol alignment while minimizing signal delay
Solution Approach 2:
The patent extracts and eliminates the need for large-scale multiplexers and extensive data buffering from the symbol alignment process. By using a simplified circuit configuration with shift registers and phase-adjusted clocks, the harmful elements (complex multiplexers and large buffers) are removed while maintaining alignment functionality
2Measurement precision
If large-scale multiplexers and data buffering are used for symbol alignment, then symbol alignment can be achieved, but device complexity increases
Solution Approach 1:
The patent changes the clock phase parameter using a phase shift frequency divider, which simplifies the overall circuit architecture. Instead of complex multiplexers and large buffers, the solution uses phase-adjusted clocks working with simple flip-flops and shift registers, thereby achieving symbol alignment with reduced device complexity
Solution Approach 2:
The patent replaces the mechanical/structural complexity of large-scale multiplexers and buffering systems with a temporal solution based on clock phase shifting. The phase shift frequency divider generates appropriately timed clocks that enable simple sequential logic elements (flip-flops) to perform the alignment function that would otherwise require complex combinatorial logic and large storage elements
Data Source
AI summary
According to an embodiment, a shift register parallelizes a serial data signal serving to transfer data including multiple symbols on the basis of a first clock. A first circuit generates, on the basis of the first clock, a second clock being a clock signal for transferring a parallel data signal having a width of the first number of bits. A first flip-flop group sequentially fetches data of the first number of bits from the serial data signals parallelized by the shift register on the basis of the second clock. The first flip-flop group then outputs the fetched data of the first number of bits as a parallel data signal. A second circuit adjusts a phase of the second clock such that the first flip-flop group fetches data of the first number of bits beginning with bit data located at a head of each symbol of the multiple symbols.