Stacked High-Voltage Memory Circuit for Core Device Protection
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Solution Overview
Problem
Memory circuits, including eFuse and anti-fuse, require high voltage for programming, which puts memory peripheral circuits and arrays under voltage stress, leading to reliability concerns with core devices failing due to lower breakdown voltages.
Innovation Solution
Implementing double or triple stack memory arrays and power switch circuits using core devices to withstand higher programming voltages without stress, along with level shifting and fractional voltage generation for stacked circuits, eliminating the need for I/O devices and reducing area and increasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to program memory cells, then programming capability is achieved, but memory peripheral circuits and arrays experience voltage stress leading to device failure
Solution Approach 1:
The patent divides the memory circuit into multiple voltage domains by stacking core devices in series (e.g., 2-stack, 3-stack configurations). Each stack handles a portion of the total high voltage, so that no single core device experiences the full breakdown voltage. This segmentation allows the memory array to operate at high programming voltages while individual devices remain within safe operating limits.
2Reliability
If I/O devices are used to handle high voltage, then voltage stress on core devices is reduced, but chip area increases
Solution Approach 1:
The patent makes core devices multi-functional by enabling them to operate in both low-voltage modes (for normal read/write operations) and high-voltage modes (for programming operations) through stacked configurations. This eliminates the need for separate I/O devices dedicated to high-voltage handling, as the same core devices perform both functions by switching between operational modes.
3Area of stationary object
If I/O devices are replaced with core devices for high voltage operation, then chip area is reduced, but core devices experience voltage stress beyond their breakdown voltage
Solution Approach 1:
By stacking multiple core devices in series, the total high voltage is divided into smaller segments across each device in the stack. For example, in a 3-stack configuration, each core device experiences approximately one-third of the total programming voltage, keeping individual device stress below breakdown thresholds while enabling the overall circuit to handle high voltages.
Solution Approach 2:
The patent changes the operational parameters of core devices by applying different voltage levels to different stacks during programming operations. By dynamically adjusting which stacks are activated and how voltage is distributed, the system enables core devices to operate reliably at elevated voltages without exceeding their individual breakdown limits.
Data Source
AI summary
One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.