Memory Receiving Circuit for Differential and Single-Ended Signals
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Solution Overview
Problem
Existing receiving circuits for semiconductor memory devices, such as DRAM, face challenges in reducing complexity and power consumption when switching between differential and single-ended modes, leading to interference and reduced accuracy in signal processing.
Innovation Solution
The proposed receiving circuit incorporates an input buffer that can operate in both differential and single-ended modes using the same transmission path, reducing interference and complexity. Additionally, the circuit adjusts current paths and load modules to minimize power consumption in single-ended mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate receiving circuits are designed for differential mode and single-ended mode, then signal processing accuracy is improved, but device complexity increases
Solution Approach 1:
The input buffer is designed to perform both differential mode reception and single-ended mode reception functions. The same buffer circuit processes signals differently based on the operating mode, eliminating the need for separate receiving circuits for each mode while maintaining signal processing accuracy
Solution Approach 2:
The circuit dynamically switches between differential mode and single-ended mode operations based on external control signals. The input buffer adapts its operation mode by responding to control inputs, allowing flexible mode transition without requiring separate dedicated circuits for each mode
2Reliability
If separate receiving circuits are designed for differential mode and single-ended mode, then signal processing reliability is improved, but ease of operation worsens
Solution Approach 1:
A single input buffer handles both differential and single-ended modes, simplifying the operational interface. Users only need to control the mode selection without dealing with separate circuit configurations, improving ease of operation while maintaining reliability through consistent circuit architecture
Solution Approach 2:
The differential mode reception and single-ended mode reception pathways are merged into a unified input buffer structure. This consolidation reduces the number of configuration parameters and control steps required, making mode switching easier while maintaining signal processing reliability
3Measurement precision
If full power is supplied in single-ended mode, then signal processing accuracy is maintained, but power consumption increases
Solution Approach 1:
In single-ended mode, the circuit applies partial power supply to the input buffer rather than full power. Since single-ended signals require less processing capability than differential signals, reduced power supply maintains adequate signal processing accuracy while significantly lowering power consumption
Solution Approach 2:
The power supply voltage parameter is dynamically changed based on the operating mode. In single-ended mode, a reduced voltage level is applied to the input buffer, optimizing the balance between signal processing accuracy and power consumption by matching the power level to the signal complexity requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the complexity and layout area of the receiving circuit, improves signal accuracy by minimizing interference, and decreases power consumption, particularly in single-ended mode operations.
Implementation Method 1
an input buffer configured to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and output a first output signal and a second output signal
Implementation Method 2
a conversion module configured to receive the first output signal and the second output signal and amplify a voltage difference between the first output signal and the second output signal
Data Source
AI summary
A receiving circuit includes: an input buffer configured to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and output a first output signal and a second output signal, where the first input signal and the second input signal are respectively a first signal and a second signal in a differential mode, the first input signal is one of the first signal and the second signal in a single-ended mode, the second input signal is a reference voltage signal, and the first signal and the second signal are complementary; and a conversion module configured to receive the first output signal and the second output signal and amplify a voltage difference between the first output signal and the second output signal.