VT-Programmable FET Memory Cells for Low-Leakage FPGA LUTs
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face challenges with look-up tables (LUTs) implemented using static random access memory (SRAM) cells, which are volatile, large, and consume significant power due to excessive leakage current, making them unsuitable for modern integrated circuit design requirements of size scaling, power scaling, and performance.
Innovation Solution
The development of a threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell, which includes a first transistor and a second transistor with electric field-based programmable threshold voltage, connected in series between voltage source lines, and a sense node at their junction, allowing for non-volatile data storage with reduced leakage and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM cells are used to implement LUTs, then data storage functionality is achieved, but power consumption increases due to excessive leakage current
Solution Approach 1:
The patent changes the fundamental parameter of memory cell type from volatile SRAM to non-volatile memory cells with electric field-based programmable threshold voltage. This parameter change eliminates continuous leakage current while maintaining data storage functionality, directly resolving the power consumption issue.
2Reliability
If SRAM cells are used to implement LUTs, then data storage functionality is achieved, but device area increases
Solution Approach 1:
The patent transitions from SRAM cell architecture to a more compact non-volatile memory cell structure with programmable threshold voltage transistors. This architectural parameter change reduces the area required per memory cell while maintaining full data storage and LUT functionality.
3Speed
If volatile memory cells are used, then fast access speed is achieved, but data retention capability deteriorates
Solution Approach 1:
The patent changes the volatility parameter from volatile to non-volatile by implementing memory cells with electric field-based programmable threshold voltage. This allows data to be retained without continuous power supply while maintaining fast access capabilities through efficient read operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of a more efficient LUT that consumes less area and power, using multiple VT-programmable FET-based memory cells in a multiplexing circuit, allowing for effective data storage and retrieval with improved performance and reduced spurious outputs.
Implementation Method 1
the gate dielectric layer of the second transistor includes a trapped electric field indicative of the stored data value
Data Source
AI summary
Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.