Two-Stage Driving Circuit for Compact 3D Memory Output Control
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Solution Overview
Problem
Planar memory cells face density limitations as feature sizes approach a lower limit, making scaling and fabrication challenging and costly, while 3D memory architectures offer a solution to increase density.
Innovation Solution
A driving circuit with a first-stage amplifier and a second-stage amplifier, including pull-up and pull-down subcircuits, utilizing multiple voltage sources to manage output voltage levels without requiring an indicator signal, reducing circuit area and elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and circuit design, then memory density increases, but fabrication becomes challenging and costly as feature sizes approach a lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked memory architecture. Multiple memory cell layers are stacked vertically, with each layer containing memory cells arranged in a planar fashion. This dimensional transition allows continued density scaling without further reducing lateral feature sizes, thereby avoiding the fabrication challenges and costs associated with sub-lithographic scaling.
2Quantity of substance
If a 3D memory architecture is implemented to address density limitations, then memory density increases, but circuit complexity increases due to additional peripheral circuits
Solution Approach 1:
The patent combines multiple amplifier functions into a single integrated amplifier circuit. The amplifier simultaneously performs differential amplification of read signals, generates feedback signals for bit line precharging, and provides driving signals for word line selection. This merging of functions reduces the number of separate peripheral circuits needed, thereby reducing overall circuit complexity despite the 3D architecture.
Solution Approach 2:
The amplifier circuit is designed with multi-functionality to handle multiple tasks: it amplifies differential read signals, generates feedback signals for bit line control, and provides driving signals for word line drivers. This universal amplifier design eliminates the need for separate dedicated circuits for each function, reducing circuit complexity while supporting the 3D memory architecture.
3Area of stationary object
If traditional amplifier circuits are used in 3D memory devices, then circuit area is larger, but power consumption increases and data transfer speed decreases
Solution Approach 1:
The amplifier circuit is segmented into distinct functional blocks: a differential amplifier stage for signal amplification, a feedback signal generation stage for bit line control, and a driving signal output stage for word line drivers. This segmentation allows each block to be optimized independently for speed and power efficiency while maintaining a compact overall layout, thereby increasing data transfer speed without proportionally increasing circuit area.
Data Source
AI summary
A driving circuit includes a first-stage amplifier circuit having a first input end receiving an input signal, a second input end receiving a feedback signal, and a first output end providing a driving signal, and a second-stage amplifier circuit having a third input end connecting the first output end to receive the driving signal, a second output end providing an output signal, and a third output end providing the feedback signal. The first-stage amplifier circuit includes a first voltage source having a first voltage level. The second-stage amplifier circuit includes a pull-up subcircuit having a fourth input end and a fourth output end, and a pull-down subcircuit having a fifth input end and a fifth output end. The fourth input end and the fifth input end connect to the third input end, and the fourth output end and the fifth output end connect to the second output end.