TDC Delay-Line Calibration for Accurate Distance Measurement
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Solution Overview
Problem
Existing distance measuring apparatuses using TDC circuits face measurement accuracy issues due to variations in delay element delay times caused by PVT variations, leading to errors in voltage drop amounts during calibration and measurement operations.
Innovation Solution
The apparatus incorporates a TDC circuit with delay elements, storage elements, an edge detection unit, and a time calculation unit to adjust the input timing of the measurement signal, utilizing a delay unit to set the detection stage earlier and reduce errors by shifting input timings across multiple channels, and employing a time/distance correction unit to refine measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If calibration operation is performed with continuous pulse input to complete quickly, then productivity is improved, but voltage drop amount increases causing measurement precision to deteriorate
Solution Approach 1:
The patent applies preliminary action by performing calibration operations before the actual distance measurement operation. The TDC circuit is calibrated in advance when voltage drop is not a critical issue, and the calibration results are stored for use during measurement. This separates the calibration process from the measurement process, allowing fast calibration without affecting measurement precision.
Solution Approach 2:
The patent implements dynamics by switching between different operational modes of the TDC circuit - calibration mode and measurement mode. During calibration, the circuit accepts continuous pulse inputs for quick characterization. During measurement, the circuit uses the stored calibration data to compensate for voltage drop effects, dynamically adapting to different operational requirements.
2Device complexity
If delay elements are used to digitize time information, then device complexity is reduced, but manufacturing precision deteriorates due to PVT variations
Solution Approach 1:
The patent applies feedback by using the calibration process to measure the actual delay amounts of delay elements and using this information to correct subsequent measurements. The system continuously monitors and compensates for PVT variations by comparing measured values against calibration references, enabling the simple delay element structure to achieve high precision through corrective feedback.
Solution Approach 2:
The patent implements parameter changes by adjusting the interpretation of delay element outputs based on calibration data. Instead of relying on fixed delay characteristics, the system dynamically adjusts the mapping between delay element stages and time values based on measured PVT conditions, allowing the same hardware to maintain accuracy across varying environmental conditions.
3Measurement precision
If bias current is adjusted to correct delay amount variability, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical/electrical adjustment approach (bias current tuning) with a computational correction approach. Instead of physically adjusting bias currents to compensate for PVT variations, the system uses calibration measurements and mathematical corrections to achieve the same effect, reducing hardware complexity while maintaining measurement precision.
Data Source
AI summary
A TDC apparatus includes a TDC circuit having a delay circuit including a plurality of stages of delay elements that sequentially delay a measurement signal, and a plurality of storage elements configured to respectively hold outputs of the plurality of stages of delay elements in response to a measurement clock input thereto, an edge detection unit configured to detect a detection stage of a delay element, among the plurality of stages of delay elements, that detects at least a rising edge of the measurement signal, based on switching of outputs of the plurality of storage elements, a time calculation unit configured to output a delay time of the measurement signal, and a delay unit configured to delay the measurement signal input thereto and input the delayed measurement signal to the delay circuit of the TDC circuit.