Neural Network Array Multiplexors for Scalable Analog Row Routing
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Solution Overview
Problem
Current artificial neural networks face challenges in achieving high-performance information processing due to inadequate hardware technology, specifically in terms of energy efficiency and scalability, as they rely on bulky CMOS analog circuits with high numbers of neurons and synapses.
Innovation Solution
The use of non-volatile memory arrays as synapses in neural networks, where each memory cell can be individually programmed, erased, and read without affecting other cells, enabling continuous analog programming and precise tuning of synapse weights, and the implementation of Vector-by-Matrix Multiplication (VMM) arrays that store weights and perform multiplication and addition functions within the memory cells, reducing the need for separate logic circuits and enhancing power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS analog circuits are used for neural networks, then high connectivity and computational parallelism can be achieved, but the circuits become bulky and energy efficiency deteriorates
Solution Approach 1:
The patent merges the synapse weight storage function with the computation function by using crossbar array memory cells to perform both roles. The memory cells store weights and simultaneously perform analog multiplication of inputs by weights through conductance modulation, eliminating the need for separate bulky CMOS analog circuits for each synapse while maintaining high connectivity.
Solution Approach 2:
The patent replaces traditional CMOS analog circuit mechanics with memory-based analog computation. Instead of using transistor-based analog multipliers and adders, the system uses memory cell conductance states to represent weights and performs multiplication through Ohm's law (I=G×V), where current through the memory cell directly represents the product of input voltage and stored weight conductance.
2Productivity
If digital supercomputers or GPU clusters are used, then high computational parallelism can be achieved, but cost increases and energy efficiency deteriorates
Solution Approach 1:
The patent implements self-service computation where the memory array itself performs the computational operations without requiring external computation resources. The crossbar array automatically performs vector-matrix multiplication through parallel current summation at the bitlines, where each memory cell contributes its weighted input current to the total sum, eliminating the need for separate CPU/GPU computation units.
3Use of energy by moving object
If non-volatile memory arrays are used as synapses, then energy efficiency and scalability improve, but additional circuitry for individual cell programming and reading is required
Solution Approach 1:
The patent makes the memory array multi-functional by enabling it to perform weight storage, weight tuning (programming), and computation (reading) all through the same memory cell structure and bitline interface. The same crossbar array used for computation can be reconfigured for weight updates by applying appropriate voltages to select specific cells for programming or erasing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise tuning of synapse weights and efficient power usage, enabling high-performance neural network operations with reduced leakage and circuitry space, improving the energy efficiency and scalability of neural networks.
Implementation Method 1
Each of the plurality of memory cells multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs
Implementation Method 2
Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 3
spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between
Data Source
AI summary
Numerous examples are disclosed of multiplexors coupled to rows in a neural network array. In one example, a system comprises a neural network array of non-volatile memory cells comprising i rows, where i is a multiple of 2; j row registers, where j<i; j digital-to-analog converters to convert j sets of digital data received from the j row registers into j analog signals; and j multiplexors to route the j analog signals to a subset of the i rows in response to a control signal.