Page Buffer Voltage Retention for Flash Programming Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory programming techniques, such as selective slow programming convergence (SSPC), while improving threshold voltage distributions, incur additional time and complexity due to the need to apportion memory cells into different subsets for each level of partial enablement.
Innovation Solution
A method that adjusts data line voltage levels during subsequent programming pulses based on the inverse relationship with NAND string current levels, using retained voltage levels from a page buffer circuit node to control source-follower transistors, thereby optimizing the programming process without the need for precise apportioning of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective slow programming convergence (SSPC) is used to improve threshold voltage distributions, then manufacturing precision is improved, but device complexity and time consumption increase due to the need to apportion memory cells into different subsets
Solution Approach 1:
The patent extracts the complex apportionment logic from the programming process by removing the need to classify memory cells into different subsets. Instead, it applies a unified programming approach where all memory cells are programmed simultaneously using the same control gate voltage, eliminating the complexity of subset management while maintaining improved threshold voltage distribution through adjusted data line voltage levels.
Solution Approach 2:
The patent inverts the traditional SSPC approach by not apportioning memory cells into subsets based on their threshold voltage characteristics. Instead, it applies the reverse strategy: all memory cells are treated uniformly during programming, but the data line voltage levels are dynamically adjusted based on the inverse relationship with NAND string current levels, achieving precision without complexity.
2Manufacturing precision
If selective slow programming convergence (SSPC) is used to improve threshold voltage distributions, then manufacturing precision is improved, but loss of time increases due to additional verify phases required for each subset
Solution Approach 1:
The patent merges the programming operations for all memory cell subsets into a single unified process. By eliminating the need to separately program and verify different subsets of memory cells, the patent reduces the total number of verify phases required. All memory cells are programmed simultaneously with adjusted data line voltage levels, and a single verify phase suffices to confirm programming accuracy across the entire array.
Solution Approach 2:
The patent maintains continuous programming action across all memory cells without interruption for subset-based verification. The unified programming approach allows the programming process to proceed continuously for all memory cells simultaneously, eliminating the time losses associated with switching between different subset programming and verification operations.
3Manufacturing precision
If data line voltage levels are adjusted based on NAND string current levels, then manufacturing precision is improved, but use of energy increases due to dynamic voltage control
Solution Approach 1:
The patent changes the voltage parameter dynamically during the programming process by adjusting data line voltage levels based on the inverse relationship with NAND string current levels. This parameter change enables precise control of charge injection into memory cells, improving programming accuracy. The voltage levels are modified in real-time according to current measurements, allowing optimization of energy usage by applying higher voltages only when necessary to achieve the desired threshold voltage distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach narrows threshold voltage distributions further, enhances programming accuracy, and reduces the complexity and time required for verify phases, improving memory density and efficiency.
Implementation Method 1
retained voltage levels from a page buffer circuit node
Implementation Method 2
control source-follower transistors, thereby optimizing the programming process
Data Source
AI summary
Memories might include a controller configured to cause the memory to precharge a data line and a node to a first voltage level, isolate the node from the data line then capacitively couple a boost voltage level to the node, selectively discharge the data line through a memory cell while applying a second voltage level to the memory cell, connect and then isolate the node and the data line, capacitively couple a deboost voltage level to the node, electrically float a control gate of a transistor that is connected to the node, connect a first source/drain of the transistor to the data line while applying a third voltage level to a second source/drain of the transistor and while electrically floating the control gate of the transistor, and apply a fourth voltage level to the memory cell while the data line is connected to the first source/drain of the transistor.