NAND Flash Discharge Circuit for Erase Voltage Stress Control
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Solution Overview
Problem
In 3D NAND flash memory, the timing of the discharge operation after an erase operation is critical to prevent source/drain junction breakdown and Fowler-Nordheim stress in the discharge transistor, which can impact performance and reliability due to high electrical potential differences and voltage stress.
Innovation Solution
A discharge circuit with a discharge transistor, a source line detect circuit, and a gate discharge circuit is implemented to maintain a constant voltage difference between the discharge transistor and the source line, ensuring the discharge transistor remains switched on while avoiding high voltage differences and using predetermined values to control the discharge process, thereby preventing junction breakdown and stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discharge transistor is used to discharge the source line and bit line after erase operation, then the discharge function is achieved, but high voltage difference causes source/drain junction breakdown and Fowler-Nordheim stress
Solution Approach 1:
A gate discharge circuit is introduced as an intermediary component between the discharge transistor gate and the source line. This circuit maintains a constant voltage difference (e.g., 5V) between the discharge transistor gate and source line, preventing excessive voltage stress on the discharge transistor while enabling safe discharge operation.
Solution Approach 2:
The voltage difference between the discharge transistor gate and source line is controlled to remain constant during discharge operation. By adjusting and maintaining this voltage parameter at a safe level (e.g., 5V), the patent prevents junction breakdown and Fowler-Nordheim stress while still achieving effective discharge.
2Ease of operation
If discharge operation is performed to release high electrical potentials, then the system returns to idle state, but improper timing causes performance degradation
Solution Approach 1:
A source line detect circuit continuously monitors the source line voltage and provides feedback control. When the source line voltage drops below a threshold (e.g., 3V), the circuit automatically turns off the discharge transistor, preventing improper discharge timing and associated performance degradation.
Solution Approach 2:
The discharge transistor is turned on before the source line voltage becomes dangerously high, and the discharge operation is initiated in advance. The source line detect circuit prepares to turn off the discharge transistor when the voltage reaches a safe threshold, ensuring proper timing without degradation.
Data Source
AI summary
The present disclosure provides a method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing an electrical potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the electrical potential of the source line is lower than the first predetermined value.