Gray Code Counter with Majority Voting for Low Memory Demand
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Solution Overview
Problem
Existing counter devices face high memory demand and error vulnerability, especially in non-volatile memories with bit-wise updates, as conventional error correction schemes are incompatible with Gray code counting, leading to inefficient memory utilization.
Innovation Solution
A method combining Gray code counting, wear levelling, and majority voting to optimize memory usage, distributing counting operations across multiple locations and using redundancy for error correction, thereby reducing memory demand and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction schemes (Hamming, BCH) are used with binary counters, then error correction capability is provided, but the number of parity bit updates equals the number of payload bit updates, eliminating Gray code advantages and increasing memory demand
Solution Approach 1:
The counter is segmented into multiple independent Gray code counters, each handling a portion of the counting bits. This segmentation allows parallel error correction processing and reduces the update burden on any single counter instance, maintaining reliability while managing memory demands efficiently.
Solution Approach 2:
An intermediary mapping layer is introduced between the Gray code counters and the error correction code (ECC) structure. This intermediary translates Gray code updates into a format compatible with conventional ECC schemes, enabling error correction without requiring parity bits to update at every counter increment, thus preserving Gray code advantages while providing reliability.
2Quantity of substance
If Gray code is used for counting, then memory demand is reduced by 50% and tearing errors are prevented, but compatibility with standard error correction schemes is lost
Solution Approach 1:
An intermediary mapping layer is introduced between the Gray code counters and the error correction code (ECC) structure. This intermediary translates Gray code updates into a format compatible with conventional ECC schemes, enabling error correction without requiring parity bits to update at every counter increment, thus preserving Gray code advantages while providing reliability.
Solution Approach 2:
The system changes the parameter representation by using Gray code for the counter bits while maintaining a separate error correction parameter space. This allows the counter to operate in Gray code mode for memory efficiency while the error correction mechanism operates independently on corrected parameters, achieving both goals simultaneously.
3Ease of operation
If binary representation is used with split high/low parts, then counting operation is simplified, but memory demand increases due to array structures
Solution Approach 1:
Instead of using binary representation with separate high/low parts and array structures, the patent inverts the approach by using Gray code with a single linear counter structure. This inversion eliminates the need for complex array indexing while maintaining counting functionality, reducing memory demand while keeping the operation simple through the natural properties of Gray code sequences.
Data Source
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AI summary
There is described a computer-implemented method of operating a counter, the method comprising: i) performing a counting operation, wherein the counting operation is done in a bit-wise manner, in particular using Gray code; ii) splitting the counting operation using a wear levelling; and iii) performing an error correction scheme with respect to the counting operation using a majority voting.