Buffer Chip Duty-Cycle Correction for Memory Strobe Synchronization

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Solution Overview

Problem

In 3D memory devices, clock synchronization issues arise due to differences in data transfer for each memory cell, while in 2D devices, uniform data clocks lead to challenges in compensating for duty cycle variations, affecting time and cost efficiency.

Innovation Solution

A memory system with a buffer chip and memory controller that performs multiple loops of duty correction on data strobe signals, including first and second loops for initial and refined corrections, and stores correction information for individual memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a uniform data clock is used for data transfer in 2D memory devices, then device complexity is reduced, but manufacturing precision deteriorates due to inability to compensate for duty cycle variations

Engineering Contradiction:

Improvedata clock structureVSAvoidduty cycle accuracy

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The patent segments the duty cycle correction process into multiple distinct loops: a first loop that performs initial duty correction during training mode, and a second loop that performs refined duty correction during normal operation. This segmentation allows each loop to be optimized for its specific function, maintaining simplicity while achieving high precision through coordinated operation of multiple specialized circuits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary duty cycle correction in the first loop during training mode before normal data transfer operations begin. This preliminary action establishes baseline correction values that are stored and used by the second loop during subsequent operations, ensuring that duty cycle accuracy is prepared in advance rather than being addressed reactively.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If multiple loops of duty correction are implemented, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:

Improveduty cycle correction accuracyVSAvoidcorrection circuit structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the functionality of multiple correction loops into a unified correction circuit architecture where the first and second loops share common components such as the duty correction unit and storage registers. This merging reduces overall device complexity by eliminating redundant circuits while maintaining the precision benefits of multi-loop correction through coordinated operation of shared resources.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The correction circuit is designed with universal components that serve multiple functions: the duty correction unit operates in both the first loop during training mode and the second loop during normal operation, and storage registers hold correction values for reuse across different operational phases. This multi-functionality reduces the need for separate dedicated circuits for each correction phase.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If duty correction is performed during training mode, then reliability is improved, but loss of time occurs during the correction process

Engineering Contradiction:

Improvedata transfer synchronizationVSAvoidtraining mode duration

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements partial duty correction during training mode by focusing the first loop on establishing baseline correction values for critical parameters rather than achieving perfect correction across all possible variations. This partial action approach achieves sufficient reliability for normal operation while minimizing the time spent in training mode, with the understanding that further refinement occurs efficiently during normal operation through the second loop.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS12586645B2Memory system, operating method of the memory system, and interface circuit of the memory system

Publication Date: 2026.03.24 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory system includes a memory device having a plurality of non-volatile memories, a buffer chip connected with each of the plurality of non-volatile memories, and a memory controller connected with the buffer chip and configured to provide a data strobe signal and a data signal to the buffer chip. The buffer chip includes a first loop coupled to a sampler circuit and configured to perform first monitoring on the data strobe signal and first duty correction on the data strobe signal based on the first monitoring, and a second loop coupled to a multiplexer and configured to, responsive to the first duty correction, perform second monitoring on the data strobe signal and second duty correction on the data strobe signal based on the second monitoring. The buffer chip is configured to store first and second duty correction information for at least one of the plurality of non-volatile memories.