Multi-Phase Memory Clock Training for Valid Window Stability
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Solution Overview
Problem
Existing memory controllers face limitations in improving high-speed operation stability due to uncorrected duty and skew distortions in multi-phase clock signals, which reduce the valid window margin for data transmission and reception.
Innovation Solution
A memory controller with a multi-phase clock generator, write clock generator, duty adjuster, and skew adjuster, which perform training operations to adjust the duties and skews of multi-phase clock signals and data, using monitoring signals and control codes to optimize clock and data characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multi-phase clock signals are used for high-speed operation, then data transmission speed is improved, but duty and skew distortions occur in the clock signals which reduces valid window margin and decreases operation stability
Solution Approach 1:
The patent performs training operations before normal data transmission to pre-adjust the multi-phase clock signals. The training circuit generates training data patterns and monitors clock signals to determine duty and skew values in advance, allowing the system to compensate for distortions before actual high-speed operation begins, thus maintaining both speed and stability
Solution Approach 2:
The patent implements a feedback mechanism where the training circuit monitors the actual clock signals during training operations, compares them against ideal waveforms, and uses the monitored duty and skew values to adjust the clock signal generation. This closed-loop feedback ensures that distortions are corrected based on actual signal characteristics, maintaining operation stability at high speeds
2Reliability
If duty and skew adjustments are made during training operation, then valid window margin is sufficient and stability is improved, but additional training processes and control operations are required
Solution Approach 1:
The patent combines multiple training functions into a single integrated training circuit that simultaneously handles duty adjustment, skew adjustment, and validation. The training circuit merges the generation of training data patterns, monitoring of clock signals, determination of duty/skew values, and adjustment operations into one unified process, reducing overall system complexity while maintaining comprehensive clock signal optimization
Solution Approach 2:
The training circuit is designed as a multi-functional unit that can perform various training operations including duty adjustment, skew adjustment, and validation of clock signals. This universal training circuit handles multiple aspects of clock signal optimization through a single integrated structure, avoiding the need for separate dedicated circuits for each function and thereby reducing device complexity
Data Source
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AI summary
The memory controller includes a multi-phase clock generator generating first to N-th clocks having N different phases, a write clock generator generating monitoring signals having a logic state corresponding to bits of the data pattern, a duty adjuster adjusting duties of the first to N-th clocks, a skew adjuster adjusting a skew of at least one of the first to N-th clocks, and a training circuit controlling a training operation for adjusting the duties and skews of the first to N-th clocks, wherein, during a first training process of adjusting the duties of the first to N-th clocks, first to N-th monitoring signals having waveforms corresponding to the first to N-th clocks are generated using data patterns having different values, and the duty of each of the first to N-th clocks is adjusted based on a result of monitoring each of duties of the first to N-th monitoring signals.