Bit Line Discharge Current Control for Flash Memory Safety
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Solution Overview
Problem
During read/program/erase operations in Flash memory, the high positive bias voltages applied to bit lines lead to peak discharge currents that exceed safety limits, causing unexpected issues due to capacitance charging and subsequent discharge, which is not effectively managed by existing technologies.
Innovation Solution
A memory device and system with a current control circuit and discharge enable circuit that control and limit the discharge current to a predefined value, eliminating peak currents and shortening discharge time by using a current mirror and staggered discharge enable signals to manage the discharge of bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high positive bias voltages are applied to bit lines during read/program/erase operations, then the memory operations can be performed, but peak discharge currents are generated that exceed safety limits
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to a predetermined voltage level before the discharge operation. The bit line discharge circuit is activated in advance to ensure that when discharge is needed, the current is already controlled within safe limits. This prevents peak current generation by preparing the discharge path beforehand through the controlled current source and transistor network.
Solution Approach 2:
The patent changes the electrical parameters of the discharge circuit by using a controlled current source that maintains constant current flow during discharge. The transistor network (including first, second, and third transistors) dynamically adjusts resistance and current characteristics to keep discharge current below safety thresholds. This parameter control transforms the uncontrolled peak current into a regulated discharge process.
2Reliability
If conventional discharge methods are used without current control, then the discharge operation is simple, but the discharge time is extended and reliability is reduced
Solution Approach 1:
The patent implements continuity of useful action by maintaining a constant controlled current throughout the discharge process. Rather than allowing intermittent or uncontrolled current flow, the controlled current source ensures continuous discharge at an optimal rate. This continuous controlled action shortens total discharge time while maintaining safety, as the current never drops to zero and then spikes, but flows steadily at a safe level.
Solution Approach 2:
The patent introduces intermediary components including the controlled current source and transistor network that mediate between the bit lines and ground. These intermediaries regulate the discharge current flow, acting as a buffer that prevents both peak currents and excessive discharge times. The intermediary circuitry ensures the discharge happens at the optimal rate for both speed and safety.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The controlled discharge current prevents peak current exceedance, ensuring safe operations and reducing discharge time, thereby enhancing the reliability and efficiency of Flash memory operations.
Implementation Method 1
A memory device and system with a current control circuit and discharge enable circuit that control and limit the discharge current to a predefined value, eliminating peak currents and shortening discharge time by using a current mirror
Implementation Method 2
The plurality of bit lines are electrically coupled to a ground voltage source to discharge the plurality of bit lines with the discharge current
Data Source
AI summary
A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. The current control circuit is coupled to the plurality of bit lines to control a discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges a charge on the plurality of bit lines.