Memory Controller Clock Training for Duty and Skew Correction
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Solution Overview
Problem
Existing memory controllers face limitations in improving the stability of high-speed operations due to uncorrected duty and/or skew distortions in multi-phase clock signals, which reduce the valid window margin for data transmission and reception.
Innovation Solution
A memory controller with a multi-phase clock generator, write clock generator, duty adjuster, and skew adjuster, which adjusts the duties and skews of multi-phase clock signals and data through a training process using monitoring signals and control codes to correct distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multi-phase clock signals are used for high-speed operation, then data transmission speed is improved, but duty and skew distortions occur causing reduced valid window margin and decreased stability
Solution Approach 1:
The patent performs duty and skew training operations before actual data transmission to pre-adjust the clock signals. The training process includes generating training data patterns, transmitting them through the interface, measuring duty and skew values, and adjusting clock generator parameters in advance to compensate for expected distortions, ensuring stable high-speed operation from the start
Solution Approach 2:
The patent implements a feedback mechanism where duty and skew values are continuously measured during training operations, and these measurements are used to adjust the clock signal parameters. The system transmits training data, receives feedback on signal quality metrics, and iteratively optimizes duty and skew values to achieve optimal timing margins for high-speed data transmission
2Device complexity
If duty and skew adjustments are not performed in the memory controller, then device complexity is reduced, but valid window margin is insufficient causing high-speed operation instability
Solution Approach 1:
The patent divides the timing adjustment function into separate duty adjustor and skew adjustor modules within the memory controller. Each module independently handles specific adjustment parameters, allowing precise control of clock signal characteristics while maintaining modular architecture that balances complexity with performance
Solution Approach 2:
The patent introduces a training operation mechanism that acts as an intermediary process between clock generation and data transmission. This training phase includes data pattern generation, signal transmission, measurement, and adjustment steps that mediate the timing synchronization between memory controller and device, ensuring valid window margins are established before actual operations
Data Source
AI summary
The memory controller includes a multi-phase clock generator generating first to N-th clocks having N different phases, a write clock generator generating monitoring signals having a logic state corresponding to bits of the data pattern, a duty adjuster adjusting duties of the first to N-th clocks, a skew adjuster adjusting a skew of at least one of the first to N-th clocks, and a training circuit controlling a training operation for adjusting the duties and skews of the first to N-th clocks, wherein, during a first training process of adjusting the duties of the first to N-th clocks, first to N-th monitoring signals having waveforms corresponding to the first to N-th clocks are generated using data patterns having different values, and the duty of each of the first to N-th clocks is adjusted based on a result of monitoring each of duties of the first to N-th monitoring signals.