Single-Poly Floating Gate Memory Cell With Tuned Channel Resistance
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Solution Overview
Problem
Conventional single-poly non-volatile memory cells have a channel resistance value for the floating gate transistor that is similar to or smaller than that of the select transistor, which can affect the efficiency of programming and erasing operations.
Innovation Solution
The memory cell design modifies the doping step to create merged n-doped regions with varying dopant concentrations, resulting in a higher channel resistance value for the floating gate transistor compared to the select transistor, enhancing programming and erasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the floating gate transistor has a similar or smaller channel resistance value than the select transistor, then the device structure is simpler and easier to manufacture, but the programming and erasing efficiency is reduced
Solution Approach 1:
The patent applies local quality by creating different dopant concentrations in specific regions. The floating gate transistor channel region is doped with a first dopant concentration while the select transistor channel region has a second dopant concentration, making them locally different to achieve the desired resistance characteristics for optimized programming and erasing efficiency
Solution Approach 2:
The patent changes the physical parameter of dopant concentration to resolve the contradiction. By adjusting the dopant concentration in the floating gate transistor channel region to be different from the select transistor channel region, the channel resistance values are optimized to improve programming and erasing efficiency while maintaining manufacturability
2Productivity
If the floating gate transistor has a higher channel resistance value than the select transistor, then electron injection and ejection efficiency is improved, but the doping process becomes more complex
Solution Approach 1:
The patent implements local quality by applying different doping conditions to different transistor channels. The floating gate transistor channel receives a first dopant concentration while the select transistor channel receives a second dopant concentration, creating localized resistance differences that enhance electron injection and ejection efficiency without requiring complete process redesign
Solution Approach 2:
The doping process is segmented into separate steps or regions. By dividing the doping operation into distinct processes for the floating gate transistor channel and the select transistor channel, the patent achieves different dopant concentrations that optimize electron transport efficiency while keeping each segment's process manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified doping process ensures that the floating gate transistor has a greater channel resistance value than the select transistor, leading to improved efficiency in programming and erasing operations by allowing for more efficient electron injection and ejection.
Implementation Method 1
The modified doping process ensures that the floating gate transistor has a greater channel resistance value than the select transistor
Data Source
AI summary
An erasable programmable single-poly non-volatile memory cell is provided. In the memory cell, plural doped regions are formed through different fabricating procedures. The memory cell includes a select transistor and a floating gate transistor. The channel length of the floating gate transistor is smaller than the channel length of the select transistor. The doping step in the manufacturing method is modified. Consequently, plural doped regions have different parameters and characteristics, and the channel resistance value of the floating gate transistor will be greater than that of the select transistor.