3D Memory Stack Row Transfer Circuit With Split Pass Transistors
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Solution Overview
Problem
The increasing demand for higher-integration semiconductor devices is limited by the need for ultra-high-cost devices for finer pattern miniaturization, and existing 2D semiconductor devices have limited applications due to their size constraints, prompting the development of 3D semiconductor devices with memory cells arranged in a three-dimensional structure.
Innovation Solution
A semiconductor device design that distributes pass transistors between a memory chip and a circuit chip, allowing for reduced size and improved high-speed performance by dividing transfer circuits between the chips, thereby reducing the number of pass transistors required per stack, regardless of the increasing number of stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a three-dimensional structure to increase integration degree, then integration density is improved, but device complexity increases
Solution Approach 1:
The transfer circuit is divided into multiple segments distributed across different chips (first chip and second chip). Each chip contains a portion of the transfer circuit, which connects row lines to global row lines. This segmentation reduces the complexity burden on any single chip while maintaining the overall 3D integrated structure.
Solution Approach 2:
The patent transitions from 2D to 3D stacking architecture, arranging memory cells in a three-dimensional structure with multiple chips stacked vertically. This dimensional change enables higher integration density by utilizing the vertical dimension, accommodating more memory cells without increasing the planar footprint.
2Quantity of substance
If the number of stacks is increased to improve integration, then capacity is improved, but the number of pass transistors per stack increases
Solution Approach 1:
The transfer circuit comprising pass transistors is segmented and distributed to multiple chips in the stack. Instead of concentrating all pass transistors in a single chip, the invention divides them between the first chip and second chip, reducing the number of pass transistors that must be managed on each individual chip while supporting an increased total number of stacks.
3Device complexity
If pass transistors are concentrated in one chip to simplify design, then device complexity is reduced, but the size of the semiconductor device increases
Solution Approach 1:
The patent utilizes 3D stacking to vertically distribute the transfer circuit across multiple chips rather than expanding it horizontally on a single chip. This vertical distribution in the third dimension reduces the planar footprint while managing the complexity through structured segmentation across the stack.
Data Source
AI summary
A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a peripheral circuit, and a second chip stacked on the first chip that is configured to include a first memory cell array and a second memory cell array. A plurality of transfer circuits are configured to connect a plurality of row lines of the first memory cell array and a plurality of row lines of the second memory cell array to respective global row lines is divided between the first chip and the second chip.