3D Memory Source-Level Structure for Isolation Trench Depth Control

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Solution Overview

Problem

Existing three-dimensional semiconductor devices face challenges in controlling the lateral isolation trench depth, which affects the electrical characteristics and reliability of vertical NAND strings.

Innovation Solution

A method involving the formation of a memory device with controlled lateral isolation trench depth is achieved by etching a sacrificial layer through a lateral isolation trench and depositing a source contact layer, followed by replacing sacrificial material layers with electrically conductive layers, creating a structure with a stepped outer sidewall and a horizontally-extending segment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the lateral isolation trench depth is not controlled, then the manufacturing process is simpler, but the electrical characteristics and reliability of vertical NAND strings deteriorate

Engineering Contradiction:

Improvereliability of vertical NAND stringsVSAvoidcomplexity of lateral isolation trench formation

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A sacrificial layer is formed at the lower source-level semiconductor layer before lateral isolation trench formation. This sacrificial layer serves as a depth reference that prevents the trench from etching too deep. After the trench is formed, the sacrificial layer is removed through the trench opening, achieving controlled trench depth without requiring complex real-time depth monitoring during etching

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer acts as an intermediary element between the etching process and the lower source-level semiconductor layer. It provides a physical barrier that mediates the interaction between the etch tool and the underlying semiconductor, ensuring the trench stops at the correct depth while allowing subsequent removal of the sacrificial material

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If dopant diffusion is not controlled, then the manufacturing process is simpler, but channel cut-off failures and gate-induced-drain leakage increase

Engineering Contradiction:

Improvereduction of channel cut-off failures and gate-induced-drain leakageVSAvoidcomplexity of dopant diffusion control

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The lower source-level semiconductor layer is structured with different thickness regions: a first portion with greater thickness and a second portion with lesser thickness. This local variation in thickness creates different dopant diffusion characteristics in different regions, allowing control over dopant distribution to prevent channel cut-off failures and gate-induced-drain leakage while maintaining manufacturing simplicity

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the electrical performance and reliability of vertical NAND strings by controlling dopant diffusion and improving etch selectivity, reducing channel cut-off failures and gate-induced-drain leakage.

Implementation Method 1

replacing the source-level sacrificial layer with at least a source contact layer by providing an etchant that etches the source-level sacrificial layer through the lateral isolation trench

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

providing a reactant that deposits the source contact layer through the lateral isolation trench

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS12538489B2Three-dimensional memory device having controlled lateral isolation trench depth and methods of forming the same

Publication Date: 2026.01.27 SANDISK TECHNOLOGIES LLC

AI summary

A memory device includes a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor layer having a surface segment that contacts the source contact layer. In one embodiment, the upper source-level semiconductor layer may be locally thickened to provide sufficient etch resistance during formation of a lateral isolation trench. In another embodiment, a sacrificial line trench fill structure may be employed as an etch stop structure during formation of a lateral isolation trench.