3D Memory Trench Isolation for Dense Vertical Cell Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory technologies face limitations in increasing storage capacity without significantly expanding footprint area, particularly in non-volatile memory solutions.
Innovation Solution
The development of a three-dimensional memory device architecture that stacks memory cells vertically, utilizing a multilayer stack with alternating dielectric layers and conductive layers, and employing a manufacturing method that includes trench formation, dielectric layer replacement, and isolation structure formation to enhance storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked memory cells are implemented, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional vertically stacked memory cells that extend in the vertical dimension rather than only lateral expansion. Multiple memory cells are stacked vertically with alternating conductive and dielectric layers, enabling increased storage capacity by utilizing the third dimension (height) of the device structure.
Solution Approach 2:
The memory device is segmented into multiple discrete memory cells arranged in vertical stacks. Each memory cell is further segmented into distinct functional layers including conductive layers for electrodes, dielectric layers for insulation, and active regions, allowing independent formation and control of each cell component through sequential processing steps.
2Reliability
If ferroelectric materials are used for data storage, then data retention without power is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs composite material structures combining ferroelectric materials with conductive and dielectric layers. The ferroelectric material is integrated into vertical memory cell stacks alongside metal conductors and insulating dielectrics, creating a multi-material composite structure that enables non-volatile data storage while maintaining compatibility with standard semiconductor manufacturing processes.
Solution Approach 2:
The patent controls critical parameters including the thickness of ferroelectric layers, composition ratios of ferroelectric materials, and dimensional tolerances of vertical stack structures. By precisely controlling these parameters during deposition and processing, the invention achieves reliable ferroelectric switching behavior and data retention while managing manufacturing complexity.
3Quantity of substance
If multilayer stacks of dielectric and conductive layers are formed, then storage capacity increases, but manufacturing process complexity increases
Solution Approach 1:
The patent forms complete vertical stacks of alternating conductive and dielectric layers through preliminary deposition processes before subsequent patterning and etching steps. This preliminary formation of full multilayer stacks simplifies later processing by establishing the complete three-dimensional structure early, reducing the need for complex sequential layer-by-layer fabrication.
Solution Approach 2:
The patent replaces traditional mechanical lithographic patterning with self-aligned formation methods where vertical stacks are defined by conformal deposition on patterned substrates. This substitution reduces alignment complexity and eliminates the need for repeated mechanical lithography steps for each layer, simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases storage capacity while maintaining a compact footprint, improving the efficiency and reliability of non-volatile memory devices by allowing for dense, vertical arrangement of memory cells and effective electrical isolation.
Implementation Method 1
incorporating ferroelectric materials for data storage
Data Source
AI summary
A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.