3D Memory Top Select Gate Segmentation for Reliability
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Solution Overview
Problem
The scaling of planar memory cells in memory devices faces challenges due to process technology limitations and reliability issues, limiting storage density and performance, which can be addressed by adopting a three-dimensional (3D) memory architecture.
Innovation Solution
A method for forming a 3D memory device involves forming an alternating dielectric stack, creating a channel structure with a memory film and channel layer, and constructing a top select gate (TSG) with a TSG dielectric and conductive layer, along with a gate line slit to enhance electrical connectivity and storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled down to reduce die size, then manufacturing cost decreases and storage density increases, but process technology limitations and reliability issues worsen
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) vertically stacked memory strings. Memory cells are arranged in vertical columns extending from the substrate, with multiple cells stacked along the vertical direction. This dimensional change enables continued scaling and increased storage density without suffering from the same process limitations and reliability degradation that plague scaled-down planar cells.
2Area of stationary object
If planar memory cells are scaled down, then die size reduction occurs, but process technology limitations worsen
Solution Approach 1:
The patent employs vertical stacking of memory cells and conductive layers along the third dimension (vertical direction) rather than continuing to scale features in the planar direction. This allows die size to be reduced while maintaining manufacturability, as the vertical architecture leverages deposition and etching processes that can achieve precise thickness control and pattern fidelity without the same scaling constraints that affect lateral dimensions.
3Reliability
If top select gate is formed continuously over memory strings, then electrical connection is established, but threshold voltage shifts occur reducing reliability
Solution Approach 1:
The top select gate (TSG) is segmented into discrete portions positioned over individual memory strings or groups of memory strings, rather than forming a continuous gate structure. Each TSG portion is separated by dielectric material, creating isolated gate regions. This segmentation prevents charge accumulation and threshold voltage shifts that would occur in a continuous gate, thereby improving reliability while maintaining the necessary electrical control over memory strings.
Data Source
AI summary
The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack that includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate; forming a channel structure penetrating through the alternating dielectric stack in a first direction perpendicular to the substrate. The channel structure includes a charge trapping layer extending in the first direction. The method also includes removing at least one second dielectric layer at a top portion of the alternating dielectric stack to form a top select gate (TSG) cut tunnel and to expose a portion of the charge trapping layer in a second direction parallel to the substrate. The method further includes removing the exposed portion of the charge trapping layer inside the TSG cut tunnel; and disposing a TSG conductive layer inside the TSG cut tunnel.