3D Memory Cell Stack with Shared Gate Deposition and Dense TSVs
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in producing a commercially viable set of master slices for various logic families, and they struggle with integrating high-density connections in 3D ICs due to the large size of Through Silicon Vias (TSVs).
Innovation Solution
The proposed method involves a 3D IC fabrication process that uses a re-programmable antifuse in conjunction with Through Silicon Via (TSV) technology to construct configurable logic devices, allowing for the creation of multiple layers with smaller, high-density connections and reducing the need for multiple mask sets by using a modular approach with repeating logic tiles and Through-Silicon-Via (TSV) connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor fabrication methods are used, then manufacturing process is well-established, but mask-set costs are high and flexibility is limited
Solution Approach 1:
The fabrication process is divided into modular stages: forming logic tiles on separate wafers, creating TSV connections, and assembling final devices. This segmentation allows independent optimization of each module and reduces the need for complete mask sets for every device variant.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical integration using Through-Silicon Vias. This dimensional change enables stacking logic tiles vertically, increasing design flexibility and reducing the number of lateral mask patterns needed.
2Quantity of substance
If Through Silicon Via (TSV) technology is used for 3D IC connections, then connection density is improved, but via size becomes large limiting further density increases
Solution Approach 1:
The connection path is segmented into multiple shorter TSV stages rather than one long via. Intermediate connection layers break the direct through-silicon path, allowing smaller individual vias while achieving the same overall connection density.
Solution Approach 2:
Connections are distributed across multiple vertical layers rather than relying on single large vias. This multi-layer approach increases connection density by utilizing the third dimension more efficiently with smaller via footprints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by minimizing the number of mask sets required and enables the production of a range of logic families with improved flexibility, while also enabling high-density connections in 3D ICs, facilitating more efficient and cost-effective production of complex semiconductor devices.
Implementation Method 1
performing at least one deposition step that simultaneously deposits gate electrodes on both the second transistors and the third transistors
Data Source
AI summary
A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.