3D Semiconductor Memory Stack With Unified Vertical Conductors
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the expensive process equipment required for fine pattern forming, hindering cost-effective increases in integration density.
Innovation Solution
A three-dimensional semiconductor memory device with a stack structure comprising electrode layers, inter-electrode insulating layers, vertical semiconductor structures, and conductive structures connected by a conductive line portion, along with a peripheral circuit and cell array structure, enhances integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density cannot be increased sufficiently
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing integration density to increase without requiring proportionally finer pattern dimensions. The stack structure includes multiple electrode layers and insulating layers stacked vertically, with memory cells formed in each layer, effectively utilizing the third dimension to achieve higher integration.
2Quantity of substance
If process equipment is upgraded to achieve finer patterns, then integration density increases, but manufacturing cost increases significantly
Solution Approach 1:
By stacking memory cell layers vertically, the patent achieves higher integration density using existing planar fabrication capabilities extended to three dimensions. This approach avoids the need for extremely expensive advanced lithography equipment while still increasing the number of memory cells per chip area. The vertical stacking allows multiple cells to share common structures, reducing overall manufacturing complexity.
Solution Approach 2:
The memory device is divided into multiple identical memory cell layers stacked vertically. Each layer can be fabricated using similar process steps, allowing for modular manufacturing. This segmentation enables increased integration through repetition of proven process modules rather than requiring entirely new fabrication techniques.
3Reliability
If vertical conductive structures and conductive line portions are separate, then manufacturing flexibility is higher, but device reliability decreases
Solution Approach 1:
The patent merges the vertical conductive structure and the conductive line portion into a single continuous conductive element. This integration eliminates the interface between separate components, removing potential failure points such as contact resistance and connection defects. The unified conductive structure provides more reliable electrical pathways while simplifying the overall device architecture by reducing the number of discrete components.
Data Source
AI summary
A three-dimensional semiconductor memory device and an electronic system including the same are discussed. The device may include: a stack structure including electrode layers and inter-electrode insulating layers that are alternately stacked on a substrate; one or more vertical semiconductor structures that extend into the stack structure and are adjacent to the substrate; one or more vertical conductive structures arranged in a first direction between adjacent ones of the one or more vertical semiconductor structures and extending into the stack structure and are adjacent to the substrate; and a conductive line portion on the stack structure that extends in the first direction to connect the one or more vertical conductive structures to each other. The conductive line portion and the vertical conductive structures may be connected to form a single unit.