3D Memory Device With Varying Buried String Heights
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Solution Overview
Problem
Existing 3D semiconductor memory architectures face limitations in compactness, which restrict further increases in data storage capacity per unit area.
Innovation Solution
A 3D memory device architecture featuring multiple 'U'-shaped strings of memory cells with buried string portions of varying heights and lengths, connected by source and bit line selector side string portions, optimized for compactness and enhanced data storage capacity, utilizing stacked word lines and selectors controlled by common signals for efficient data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D memory structure is used, then manufacturing process is simple, but data storage capacity per unit area is limited
Solution Approach 1:
The patent transitions from traditional 2D memory architecture to a 3D vertical architecture where memory cells are stacked in multiple layers above the substrate. This dimensional change enables significantly increased storage capacity per unit area by utilizing the vertical space rather than only horizontal plane, resolving the contradiction between storage capacity and area utilization.
Solution Approach 2:
The patent implements a nested structure where multiple buried string portions are positioned at different heights within the substrate, and memory cell stacks are arranged vertically above them. This nesting approach allows multiple memory cell layers to occupy overlapping horizontal footprints, thereby increasing storage density without proportionally increasing the device footprint.
2Area of stationary object
If memory cells are arranged in single layer (2D), then area utilization is low, but manufacturing precision requirements are lower
Solution Approach 1:
The patent segments the memory structure into multiple independent layers, with each layer containing buried string portions and memory cell stacks. This segmentation allows each layer to be manufactured and aligned independently, reducing the cumulative alignment precision requirements compared to forming all structures in a single complex process step.
Solution Approach 2:
The patent forms the buried string portions in the substrate at different heights as preliminary structures before stacking the memory cells above them. This preliminary action establishes precise vertical reference positions that guide subsequent memory cell formation, ensuring proper alignment without requiring extremely high precision in all subsequent steps.
3Volume of moving object
If buried string portions are at same height with same length, then manufacturing is simple, but compactness is reduced
Solution Approach 1:
The patent applies local quality by varying the lengths and heights of buried string portions at different locations within the substrate. Instead of uniform strings throughout, each buried string portion is customized in length and position to optimize the overall packing efficiency and compactness of the memory structure, allowing denser arrangement of memory cell stacks.
Solution Approach 2:
The patent introduces asymmetry in the buried string portion configurations, with strings at different heights and different lengths rather than symmetric uniform structures. This asymmetric arrangement enables more efficient space utilization and better compactness by fitting memory cell stacks into irregular gaps and optimizing vertical stacking patterns.
Data Source
AI summary
A 3D memory device comprising: a substrate; at least three first “U”-shaped strings of memory cells each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped string of memory cells including stacks of memory cells along the first source line selector string side portion and along the first bit line selector side string portion; and at least three second “U”-shaped strings of memory cells each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line selector side string portion, each of the second “U”-shaped string of memory cells including stacks of memory cells along the second source line selector side string portion and along the second bit line selector side string portion. The first buried string portions are formed at mutually different heights in the substrate and they have mutually different lengths, and the second buried string portions are formed at mutually different heights in the substrate and they have mutually different lengths. The first and second source line selector side string portions are between the first and second bit line selector side string portion.