3D Non-Volatile Memory With Vertical Bit Lines
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Solution Overview
Problem
Existing two-dimensional arrays of variable resistance memory elements face challenges in reducing leakage currents and complexity, leading to inaccurate data reading and increased power consumption due to the need for diodes and complex manufacturing processes.
Innovation Solution
A three-dimensional array architecture with vertically oriented bit lines and select devices, eliminating the need for diodes by sharing common bit lines across multiple planes, reducing leakage currents, and simplifying manufacturing through fewer masks and processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If diodes are connected in series with variable resistive memory elements to reduce leakage currents, then leakage current is reduced, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent removes diodes from the memory cell structure entirely. By using a three-dimensional cross-point architecture where bit lines and word lines intersect vertically, the invention achieves leakage current control without requiring additional diode components, thus simplifying the device while maintaining the ability to control harmful leakage currents through selective voltage application.
Solution Approach 2:
The patent transitions from a two-dimensional memory array to a three-dimensional cross-point architecture. This dimensional change allows bit lines to extend vertically through multiple planes, enabling selective addressing of memory elements without requiring diodes. The vertical intersection of bit lines and word lines creates a more efficient structure that reduces leakage paths while simplifying the overall device complexity.
2Object-generated harmful factors
If diodes are connected in series with variable resistive memory elements to reduce leakage currents, then leakage current is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent eliminates the need for diodes in the memory cell structure by adopting a three-dimensional cross-point architecture. This extraction of unnecessary components directly reduces manufacturing complexity, as fewer material deposition steps, patterning operations, and alignment processes are required compared to structures that incorporate diodes.
Solution Approach 2:
By moving to a three-dimensional architecture where conductors intersect vertically, the patent simplifies manufacturing. The vertical bit lines can be formed as continuous structures through multiple planes, reducing the number of processing steps and masks needed compared to two-dimensional arrays that require diode integration.
3Productivity
If reading or programming voltages are applied to a large number of memory elements in parallel, then data reading and programming operations are performed efficiently, but power consumption increases
Solution Approach 1:
The patent divides the memory array into multiple planes with vertically extending bit lines that can be selectively activated. This segmentation allows only the specific memory elements at the intersection of selected bit lines and word lines to be accessed, while other elements remain inactive. Consequently, voltage is applied only to the necessary subset of memory elements, maintaining high productivity while reducing overall power consumption compared to applying voltages to all elements in parallel.
Data Source
AI summary
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.