3D Memory Array with Vertical Bit Lines and Single-Sided Word Line
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory systems face challenges in reducing the size and cost of memory cell arrays while minimizing leakage currents and manufacturing complexity, particularly in three-dimensional arrays where unaddressed memory elements are affected by programming and reading operations.
Innovation Solution
A three-dimensional memory array architecture with vertically oriented bit lines and a double-global-bit-line or single-sided word line configuration, which reduces leakage currents by allowing only selected memory elements to be addressed directly, eliminating the need for diodes and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional two-dimensional flash memory arrays are used, then manufacturing processes are well-established, but leakage currents affect unaddressed memory elements and increase power consumption
Solution Approach 1:
The patent transitions from conventional two-dimensional memory arrays to a three-dimensional architecture where bit lines extend vertically through multiple planes. This dimensional change allows selected memory elements to be directly addressed while unselected elements remain isolated, eliminating leakage currents without requiring additional diode structures.
2Loss of energy
If diodes are added to memory elements to reduce leakage currents, then leakage is minimized, but manufacturing complexity and processing steps increase
Solution Approach 1:
The patent extracts the diode component from the memory element structure entirely. By using vertical bit lines that pass through insulating layers to directly access memory elements in selected planes, the architecture achieves leakage current reduction without requiring diodes, thereby simplifying the manufacturing process.
3Quantity of substance
If more memory elements are packed into the array to increase capacity, then storage density improves, but leakage currents and manufacturing errors increase
Solution Approach 1:
The three-dimensional architecture with vertical bit lines extending through multiple planes allows for increased memory element density while maintaining reliability. The vertical configuration enables precise addressing of selected elements, preventing leakage-induced errors even as the total number of memory elements increases across multiple planes.
Data Source
AI summary
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.