Nanoinformatics TRIZ Cases

Selective oxidation forms dielectric layers on nanowire sidewalls to reduce parasitic capacitance in horizontal gate-all-around transistors.

Fluorine surfactant gradient lowers mold release force, resolving pattern defects during photo-nanoimprint demolding.

A semiconductor process forms NVM cells and logic transistors using metal nanocrystals and high-k gate dielectrics.

Gate-all-around nanowires improve electrostatic control during aggressive gate length scaling.

A carbazole compound with high electron affinity acts as a charge blocking layer in photoelectric conversion devices.

Single crystal silicon pellicles overcome low transmittance and oxidation issues in EUV lithography through porous support structures.

A measurement device detects mold and substrate marks in a non-contact state to enable precise alignment control.

Non-selective etch creates metal gate cuts and recessed power rails, resolving accuracy issues in conventional mask-based decoupling methods.

Segmented gates and insulating material isolate quantum dots in a well stack, resolving the trade-off between precise control and array scalability.

Scanning an alignment radiation beam detects intensity changes from template marks to resolve manufacturing cost and precision trade-offs.

A doped nucleation layer enables selective backside silicon etching to isolate nanoribbon sub-fins in advanced integrated circuit structures.

Antiparallel shield structure decouples electroplated layers from ferromagnetic films to minimize hysteresis and reduce noise during read operations.

Segmented inner spacers resolve manufacturing precision limits to improve semiconductor reliability.

Segmented metal silicide liners reduce middle-of-line contact resistance in advanced CMOS devices without increasing device complexity.

Two-phase thermal synthesis produces cadmium sulfide quantum dots with narrow size distribution and high photoluminescence efficiency.

A bulk heterojunction layer combines a polymer n-type semiconductor with a fullerene network and a low molecular weight p-type material.

Chemical mechanical polishing and etching back interlayer dielectrics improve thickness uniformity of isolation layers in vertical semiconductor devices.

A composite electron injection layer uses crown ether-grafted conjugated polymers to facilitate charge transport.

Segmented absorber layers reduce critical dimension bias during extreme ultraviolet mask fabrication.

Titanium nitride resonators suppress parasitic two-level systems to maintain high quality factors at low field levels.

Dissimilar materials enable Seebeck-driven heat redistribution, allowing precise hot spot positioning within nanoheaters for thermal recording.

Tunneling field effect transistors replace thermionic emission with quantum tunneling, achieving subthreshold swings below 60 millivolts per decade.

Sweeping a temperature zone across self-assembled polymer layers reduces defect rates caused by incomplete alignment during annealing.

Amorphous carbon sacrificial mask prevents mini spacer formation and plasma damage on silicon nanowires during fabrication.

Vertical bit lines through multiple planes address selected memory elements directly, eliminating leakage currents without requiring diodes.

A resistive random access memory storage node uses a metal compound first electrode to regulate ion transport within the solid electrolyte layer.

Epitaxial growth on a mandrel sidewall controls channel thickness, overcoming photolithography limits to boost integration density.

A method for forming a qubit device using epitaxial growth to create a semiconductor channel structure over an embedded gate electrode.

A gate zero template acts as a self-aligned mask to define precise gate spacing, reducing charge noise and process complexity.

Epitaxial isolation layers shield source-drain regions from etching damage during sacrificial nanosheet removal, preserving device integrity.

Trenched bottom electrode structures facilitate scalable fabrication of molecular spintronics devices with improved spin coherence and reduced heat damage.

Sidewall ion implantation prevents parasitic epitaxial growth below bottom dielectric isolation in nanosheet transistors.

Ion implantation forms self-aligned source and drain contacts in double gate FETs, resolving complex junction formation challenges.

Fabrication method for surrounding gate silicon nanowire transistors using air spacers to lower parasitic capacitance.

Recursive region division splits high-density areas to maintain uniformity in low-density zones, resolving material distribution precision challenges.

Replacing Al-rich barriers with GaSb materials reduces leakage currents and carbon incorporation while maintaining electron confinement.

Position-dependent switching layer resistance compensates for conductive path voltage drops, ensuring uniform internal voltages across all memory elements.

A nanosheet structure uses segmented work function conducting layers to define distinct inner and outer regions for precise electrical control.

Piezoelectric and pneumatic actuators position an imprint template to correct thermal expansion errors in lithography.

Selective etching widens gate gaps to prevent pinch-off during inner spacer deposition, ensuring reliable epitaxial growth at scaled pitches.

Light scattering measurement distinguishes actual mold abnormalities from substrate defects, reducing unnecessary removal and improving production yield.

Intermediate layers facilitate hole and electron transport between buffer layers and electrodes in organic optoelectronic devices.

Feedback control maintains consistent voltage across the nanowire, preventing thermal runaway during Joule heating induced state transitions.

A layer structure with a strain-inducing layer applies mechanical stress to a channel layer to boost carrier mobility in electronic devices.

Segmenting analog and digital regions on a chip resolves the trade-off between transistor density and RF performance.

A manufacturing method for sub-wavelength gratings uses segmented sacrificial photoresist layers to define precise cavity structures.

Antiferromagnetically coupled ferromagnetic layers stabilize the magnetic moment, reducing noise and improving processing margin.

Dynamic pressure roller control varies velocity and force across the mold to resolve non-uniform residual film thickness in display device manufacturing.

A semiconductor apparatus uses a comb-like channel structure to enhance current driving capability and mechanical stability.