Isolation Layer Formation in Vertical Semiconductor Devices

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Solution Overview

Problem

Vertical semiconductor devices face challenges in achieving uniform thickness control of inter-layer dielectrics due to low pattern density, which affects device performance.

Innovation Solution

The method involves forming an isolation layer through various schemes, including deposition, chemical mechanical polishing (CMP), and etching techniques, using layers such as ONO (oxide/nitride/oxide) and gas cluster ion beams to achieve uniformity, applicable to source, channel, and drain isolation layers in vertical structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional deposition and planarization methods are used for inter-layer dielectric in vertical semiconductor devices, then the manufacturing process is simple, but the thickness uniformity of isolation layer deteriorates due to low pattern density

Engineering Contradiction:

Improvethickness uniformity of isolation layerVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The isolation layer formation is divided into multiple stages: initial deposition of inter-layer dielectric material, selective removal in patterned regions, and subsequent planarization. This segmentation allows precise control of thickness in different regions, addressing the low pattern density issue by treating high-density and low-density areas differently through staged processing

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A preliminary deposition step is performed to form the inter-layer dielectric layer before final planarization. This preliminary layer provides a foundation that can be selectively modified in patterned regions, enabling subsequent thickness uniformity control without requiring complete re-deposition across the entire wafer

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If additional layers and processing steps are added to improve thickness uniformity, then the thickness uniformity of isolation layer improves, but the device complexity increases

Engineering Contradiction:

Improvethickness uniformity of isolation layerVSAvoidmanufacturing efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The additional layers (such as mandrel layers and fill layers) serve multiple functions: they act as structural support during processing, define pattern regions for selective removal, and provide material for planarization. This multi-functionality reduces the need for separate dedicated process steps, maintaining productivity while improving thickness uniformity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances thickness uniformity of isolation layers, improving device performance by ensuring consistent wafer and die uniformity across different semiconductor devices.

Implementation Method 1

performing a chemical mechanical polishing (CMP) on the first interlayer dielectric

Methodology Applied

Scientific EffectChemical mechanical polishing:

Implementation Method 2

etching techniques, using layers such as ONO (oxide/nitride/oxide) and gas cluster ion beams

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS11227788B2Method of forming isolation layer

Publication Date: 2022.01.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.