NVM and Logic Integration Using Metal Nanocrystals
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Solution Overview
Problem
Integrated circuits with both non-volatile memories (NVMs) and logic devices face challenges in achieving high performance without sacrificing logic performance or increasing costs.
Innovation Solution
A semiconductor manufacturing process that contemporaneously forms NVM cells and logic transistors using high-k gate dielectrics, metal gates, and metal nanocrystals, employing a replacement gate process to optimize both components while minimizing additional costs and thermal stress on high-k materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NVM and logic are integrated on the same chip, then functionality and application versatility are improved, but logic performance deteriorates due to resource sharing and design compromises
Solution Approach 1:
The patent divides the integrated circuit into distinct NVM regions and logic regions with separate processing optimization. The NVM cells use specific structures (tunnel oxide, charge storage layer, control gates) while logic regions use optimized transistor designs, allowing each segment to be tuned for its specific function without compromising the other.
Solution Approach 2:
Different material layers and structural configurations are applied locally to different regions of the chip. The NVM region receives specialized dielectric layers and gate structures while logic regions receive different optimizations, enabling each area to have the quality characteristics needed for its specific function.
2Speed
If advanced processing techniques are used to achieve high performance for both NVM and logic, then performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines NVM cell formation and logic transistor formation into a single integrated process flow using common processing steps where possible. Both NVM and logic regions share the same substrate processing, doping steps, and interconnect formation, reducing the need for separate manufacturing lines and lowering overall production costs.
Solution Approach 2:
The patent uses universal processing techniques that serve both NVM and logic fabrication. The same basic transistor structure formation, gate dielectric deposition, and source/drain processing are applied to both NVM select transistors and logic transistors, creating a multi-functional manufacturing approach that reduces complexity and cost.
3Speed
If high-k gate dielectrics are used to improve NVM performance, then NVM performance is improved, but thermal stress and material integrity deteriorate due to exceptionally high temperatures required for processing
Solution Approach 1:
The patent modifies processing parameters to achieve adequate NVM performance without requiring exceptionally high temperatures. By adjusting doping concentrations, gate dielectric thickness, and charge storage layer composition, the patent achieves high NVM performance at moderate temperatures that preserve high-k material integrity and reduce thermal stress.
Solution Approach 2:
The patent uses composite structures combining high-k gate dielectric materials with carefully engineered charge storage layers and tunnel oxides. This composite approach allows the system to achieve high NVM performance through the synergistic properties of multiple materials rather than relying solely on extreme temperature processing of single materials.
Data Source
AI summary
A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.