Nanoribbon Sub-fin Isolation via Backside Etch Selectivity
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Solution Overview
Problem
The challenge in fabricating integrated circuit structures, particularly for multi-gate and nanowire transistors, is the trade-off between the critical dimension of patterned features and the spacing between them, which becomes overwhelming as dimensions scale below the 10 nanometer node.
Innovation Solution
The implementation of a backside substrate removal etch selective to source and drain epitaxy using a doped nucleation layer at the base of the epitaxy, which helps in controlling the silicon etch during the backside reveal process and reduces the risk of etching out the epitaxial structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the critical dimension of patterned features is reduced to increase device density, then the spacing between features must also be reduced, but this makes lithographic patterning increasingly difficult and constrained
Solution Approach 1:
The patent introduces a vertical dimension by forming nanowire structures that extend through the substrate thickness, enabling device differentiation along the vertical axis rather than solely relying on horizontal feature spacing. This dimensional transition allows higher device density without proportionally reducing lateral feature dimensions, thereby maintaining lithographic patterning feasibility.
Solution Approach 2:
The patent inverts the conventional approach by removing substrate material from the backside to reveal and access nanowire structures, rather than patterning features from the front surface. This backside removal technique enables precise definition of active regions and electrical contacts without being constrained by front-side lithographic resolution limits.
2Ease of manufacture
If conventional front-side patterning is used to define features, then lithographic constraints limit the minimum feature size and spacing, but backside substrate removal enables access to nanowire structures without these constraints
Solution Approach 1:
The patent performs substrate removal from the backside opposite to the conventional front-side patterning approach. This inversion allows the nanowire structures to be defined by the etch stop layer geometry rather than direct lithographic patterning, achieving precise feature definition through self-aligned processes and eliminating minimum feature size constraints.
Solution Approach 2:
The patent introduces an etch stop layer as an intermediary element that mediates between the substrate and the nanowire structures. This intermediate layer enables selective removal of substrate material while preserving the nanowire structures, achieving precise feature definition through material selectivity rather than direct lithographic patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control over the substrate removal, reducing the risk of etching errors and enabling more flexible device performance metrics, thereby addressing the challenges of scaling in integrated circuit fabrication.
Implementation Method 1
backside substrate removal etch selective to source and drain epitaxy
Data Source
AI summary
Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires; and a doped nucleation layer at a base of the epitaxial source or drain structures adjacent to the sub-fin. Where the integrated circuit structure comprises an NMOS transistor, doped nucleation layer comprises a carbon-doped nucleation layer. Where the integrated circuit structure comprises a PMOS transistor, doped nucleation layer comprises a heavy boron-doped nucleation layer.