3D Semiconductor Memory Vertical Channel Structure for Higher Density
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Solution Overview
Problem
Current semiconductor devices face limitations in integration density due to high costs associated with micropatterning technologies, necessitating the development of three-dimensional semiconductor memory devices with improved electrical characteristics.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a substrate, alternately stacked interlayer dielectric layers and gate electrodes, featuring vertical channel structures that include a data storage pattern with a ferroelectric material, a vertical channel pattern of oxide semiconductor material, and a conductive pad, allowing for enhanced integration density and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three-dimensional semiconductor memory device is designed with vertical channel structures including oxide semiconductor material and ferroelectric material, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The vertical channel structure is segmented into distinct functional layers: oxide semiconductor material layer for channel formation, ferroelectric material layer for data storage, and conductive pad for electrical connection. This segmentation allows each layer to be optimized independently for its specific function, improving overall electrical characteristics while maintaining manageable device complexity through modular design
Solution Approach 2:
The patent employs a nested structure where the conductive pad is positioned within the vertical channel structure, specifically with the oxide semiconductor material surrounding the conductive pad and the ferroelectric material layer positioned above. This nested arrangement integrates multiple functional elements in a compact vertical configuration, improving electrical characteristics by reducing resistance and enhancing coupling while controlling device complexity through spatial efficiency
2Productivity
If integration density is increased through three-dimensional structure, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional vertical channel structures, stacking interlayer dielectric layers and gate electrodes vertically. This dimensional change increases integration density by utilizing the vertical space above the substrate, allowing more memory cells to be packed into the same footprint while managing manufacturing precision through standardized layer thicknesses and alignment features
Solution Approach 2:
The patent employs composite material structures combining interlayer dielectric layers with gate electrodes in alternating stacks, and combines oxide semiconductor material with ferroelectric material in the vertical channel. These composite structures enable enhanced electrical characteristics and improved integration density while managing manufacturing precision through established deposition and patterning processes for each material type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased integration density and improved electrical characteristics, such as enhanced transistor performance and hole injection capabilities, while reducing the need for expensive micropatterning equipment.
Implementation Method 1
a data storage pattern conformally covering an inner sidewall of the channel holes and having a single-layer structure including a ferroelectric material
Implementation Method 2
a vertical channel pattern covering a sidewall of the data storage pattern and including an oxide semiconductor material
Data Source
AI summary
Provided are a three-dimensional semiconductor memory device, a method for manufacturing the same, a method for operating the same, and an electronic system including the same. The three-dimensional semiconductor memory device includes a substrate, a stack structure on the substrate, and vertical channel structures, which are provided in channel holes penetrating the stack structure, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, a conductive pad, and a vertical semiconductor pattern, wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern, and wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween.