3D Memory Device Vertical Channel Pillar Stacking
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Solution Overview
Problem
Three-dimensional (3D) memory devices with vertical channel structures face challenges in achieving high storage density and efficient area utilization, as existing technologies struggle to effectively stack memory cells while maintaining compatibility with existing fabrication processes.
Innovation Solution
A 3D memory device design featuring vertically stacked memory cells with a specific configuration of bit lines, word lines, source lines, and charge storage structures, along with a method of fabrication that includes forming channel pillars and charge storage structures on a dielectric layer, allowing for efficient use of substrate area and compatibility with existing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D memory devices with vertical channel structures are designed to increase storage density, then storage capacity is improved, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is divided into multiple cycles, with each cycle forming a subset of memory cells. The charge storage structure is segmented into upper and lower portions separated by a source line, allowing independent formation and control of different memory cell components through repeated application of the same fabrication cycle
Solution Approach 2:
The patent transitions from two-dimensional planar gate structures to three-dimensional vertical channel structures with charge storage structures extending along the vertical dimension. Memory cells are stacked vertically with channel pillars extending in the third dimension, enabling higher storage density by utilizing vertical space rather than only horizontal plane
2Area of stationary object
If memory cells are stacked vertically to utilize substrate area effectively, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The charge storage structure is formed on the sidewall of the channel pillar before the source line is created. This preliminary formation ensures proper positioning and alignment, as the charge storage structure serves as a template that guides subsequent source line formation and maintains precise vertical relationships throughout the fabrication process
Solution Approach 2:
The charge storage structure is formed by depositing material on the sidewall of the channel pillar, creating a nested configuration where the charge storage structure surrounds the channel pillar. This nested approach ensures precise alignment and positioning through conformal deposition, maintaining manufacturing precision while enabling vertical stacking
Data Source
AI summary
A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.