Solid-State Devices TRIZ Cases

Vertical channel pillars penetrate stacked word lines to boost storage density while maintaining fabrication process compatibility.

A diffusion barrier pattern prevents metal atom migration between the bottom electrode and seed layer.

A dibenzoborole-based compound acts as a p-dopant in the hole transport layer to lower the injection barrier at the anode interface.

A concave geometry with reflective surfaces and index-matching material overcomes total internal reflection limits in OLEDs.

Selective epitaxial silicon growth fills memory array trenches with in-situ doping to form conductive bitlines.

Modifying chemical structures of organic semiconducting polymers improves power conversion efficiency while maintaining cost advantages.

An OLED structure employs asymmetric host materials to disperse the recombination region and minimize luminance degradation over time.

A resonator structure positions a blue light emitting layer at a specific optical distance to intensify blue emission.

A native metal oxide layer grown at 250°C or less between redistribution lines and passivation layers prevents copper migration without cracking the oxide film.

A flexible organic light emitting display device integrates thin film encapsulation layers directly onto a polarization plate to seal the panel.

A single pixel with vertically overlapping photoelectric conversion parts detects various wavelength ranges using one transfer gate.

Epitaxial growth of III-V structures on silicon substrates enables precise collective transfer, reducing misalignment costs.

Tilted light guides direct oblique light to offset pixels, reducing cross-talk and boosting quantum efficiency.

Segmented permanent magnets connected by conductive elements create a homogeneous field, reducing thermal susceptibility and manufacturing tolerance issues.

Vertical transistors function as both select devices and peripheral circuit elements, reducing chip area by eliminating dummy structures.

Integrating a two-terminal resistor structure into resistive switching memory cells reduces programming currents, minimizing power consumption and cross-talk.

Integrating a touch sensor with a display panel via direct PCB connections reduces device thickness and improves sensing accuracy.

Metal phthalocyanine monolayers functionalize inert 2D semiconductor surfaces to enable uniform atomic layer deposition of dielectric oxides.

Segmented stepped surfaces resolve the trade-off between processing complexity and electrical contact capability in high-density 3D memory devices.

Metal silicide layers contacting trench sidewalls reduce buried bit line resistance, enabling high-speed operation without expanding unit cell area.

An extended reflector captures diverging light rays that would otherwise escape, enabling high focussing efficiency within a compact collimator volume.

Segmenting the manufacturing process with sacrificial material reduces etch damage and contamination during memory cell formation.

Controlling the exterior angle of the element active layer within 55° to 75° removes surface defects, enhancing luminous efficiency and display quality.

Hexagonally closest packed semiconductor pillars electrically couple to bitlines and drain-side select gates.

Subwindowing and subsampling reduce readout time, maintaining measurement accuracy during high angular velocity tracking.

Integrating light emission and sensing into one pixel eliminates separate circuits, reducing device weight while maintaining multifunctionality.

Flip-chip mounted ultraviolet light source emits radiation directly onto a computer chip to erase memory areas within the system on chip.

A UV LED package uses a ceramic body cavity with a dedicated heat dissipation member and buffer layer to manage thermal loads.

Introducing a high-resistance separator in OLED corners redistributes current to prevent hot spots without altering device geometry.

A pixel structure places a common line between the data line and pixel electrode to reduce capacitance coupling.

Opaque barrier between packaged light source and detector minimizes optical crosstalk while maintaining compact module size for portable applications.

Segmenting the protection circuit with a crowbar device prevents data loss from increased capacitance while sustaining high currents without premature failure.

A lift-off process removes masking patterns and anti-decapping layers to simplify organic light-emitting display manufacturing.

Dual word line phase change memory architecture segments access transistors to reduce reset voltage requirements while maintaining high array density.

Laser ablation creates shield tunnels in single-crystal silicon, enabling plasma etching of device chips with high flexural strength.

A MIS storage capacitor uses a P-Si semiconductor layer to accumulate holes under negative voltage and form a depletion layer under positive voltage.

Segmented upper electrode layers allow targeted particle removal during repair, maintaining optical characteristics without thick single-layer constraints.

Overlapping wire segments in the non-display area increase stress at connection points, enabling accurate crack detection and preventing moisture ingress.

A buried guard ring structure enhances electrical conductivity to resist ionizing radiation in standard CMOS fabrication.

A selective light transmittance layer increases non-target wavelength transmission in organic photoelectronic devices.

A segmented organic light-emitting display panel uses distinct hole and electron mobility ratios in stacked layers to optimize charge carrier recombination.

Pushing the third outer surface of a resin molded package removes it from a lead frame without applying bending force that damages the housing.

A static random access memory cell uses distinct lightly-doped drain dosages to control transistor current flow.

A thermal sublimation method transfers organic light emitting materials using a temporal transfer substrate and localized heating to form precise pixel patterns.

Narrowing the hard mask in low-density regions compensates for loading effects to minimize final inspection critical dimension differences.

A MOSFET with an integrated p-n junction clamping diode absorbs low avalanche current to protect the active area.

Polygonal electrode geometry reduces the contact area with phase change material layers, lowering reset current while maintaining electrical reliability.

Reverse-biased pn junction in photo-detector reduces bulk leakage current, lowering power consumption for TOF imaging.

A protective member extends beyond the sealing resin on a flexible substrate to shield electronic components from external forces.