Selective Epitaxial Bitline Formation for Flash Memory
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Solution Overview
Problem
Conventional bitline formation processes in memory arrays, such as flash memory, cause lateral dopant diffusion and transient enhanced diffusion, leading to reduced effective channel length and increased short channel effects like punch through and drain induced barrier lowering (DIBL).
Innovation Solution
The method involves forming trenches in a substrate with an ONO stack and using selective epitaxial growth of silicon to fill these trenches, followed by a silicon reflow process to redistribute the silicon, thereby forming bitlines without the need for dopant implantation and annealing, which reduces lateral diffusion and transient enhanced diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopant implantation and anneal process are used to form bitlines, then bitlines can be formed with activated dopant, but lateral diffusion of dopant into channel region occurs causing reduced effective channel length
Solution Approach 1:
The patent changes the fundamental parameter of dopant introduction method from implantation to in-situ doping during selective epitaxial growth. This parameter change eliminates the transient enhanced diffusion effect that occurs with implantation followed by annealing, thereby preventing lateral dopant diffusion and maintaining precise effective channel length while still achieving activated dopant in the bitline region
Solution Approach 2:
The patent replaces the mechanical/physical implantation process with a chemical vapor deposition process (selective epitaxial growth) where dopants are introduced during silicon growth. This substitution eliminates the crystal structure damage caused by implantation that leads to TED, achieving both bitline formation and precise channel length control
2Stability of the object's composition
If anneal process is used to repair crystal structure damage, then crystal structure is repaired, but transient enhanced diffusion increases lateral dopant diffusion
Solution Approach 1:
The patent performs preliminary doping during the selective epitaxial growth process itself, before any annealing step is needed. The dopants are incorporated into the silicon crystal structure during growth, eliminating the need for subsequent annealing to activate dopants or repair damage, thereby avoiding transient enhanced diffusion entirely
Solution Approach 2:
The patent extracts or removes the annealing step from the bitline formation process by using in-situ doping during selective epitaxial growth. Since dopants are already activated during growth, the harmful annealing step that causes TED and lateral diffusion is eliminated while still achieving the desired crystal structure and dopant activation
3Ease of manufacture
If conventional bitline implantation process is used, then bitlines are formed, but lateral straggle and transient enhanced diffusion increase short channel effects
Solution Approach 1:
The patent changes the process parameter from dopant implantation to in-situ doping during selective epitaxial growth. This parameter change maintains ease of manufacture through a standardized CVD process while eliminating lateral straggle and TED, thereby reducing short channel effects and improving device reliability
Solution Approach 2:
The patent substitutes the implantation-based mechanical process with a chemical vapor deposition process for selective epitaxial growth. This substitution maintains manufacturing simplicity while eliminating the physical damage and subsequent TED that cause lateral straggle and short channel effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents lateral straggle and transient enhanced diffusion, maintaining the effective channel length and reducing short channel effects, while also simplifying the process by eliminating the need for dopant implantation and annealing, thus decreasing process steps and costs.
Implementation Method 1
performing a selective epitaxial process to partially fill the trench with selective epitaxially grown silicon, where the selective epitaxially grown silicon is situated on the sidewalls and bottom surface of the trench
Implementation Method 2
performing a silicon reflow process, where the silicon reflow process causes the selective epitaxially silicon to be redistributed in the trench
Data Source
AI summary
According to one exemplary embodiment, a method of fabricating a bitline in a memory array includes forming a trench in a substrate, where the trench has sidewalls and a bottom surface. The method further includes performing a selective epitaxial process to partially fill the trench with selective epitaxially grown silicon, where the selective epitaxially grown silicon is situated on the sidewalls and bottom surface of the trench. The selective epitaxially grown silicon is doped in the selective epitaxial process. The method further includes performing a silicon reflow process to cause the selective epitaxially silicon to be redistributed in the trench. The method further includes performing a number of selective epitaxial process/silicon reflow process cycles to substantially fill the trench with the selective epitaxially grown silicon. The method further includes extending a top surface of the selective epitaxially grown silicon in the trench above an ONO stack to form the bitline.