Hard Mask Width Variation for Etch Loading Compensation
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Solution Overview
Problem
The reduction of critical dimension (CD) in semiconductor devices, particularly in peripheral regions with lower pattern density, is hindered by the loading effect during the etching process, leading to increased final inspection CD differences and pattern failures due to the hard mask scheme, which complicates photolithography and pattern formation.
Innovation Solution
A method is introduced where a substrate with distinct pattern density regions undergoes a process of forming hard mask patterns with reduced widths in the peripheral region, using these reduced hard mask patterns as etch barriers to minimize the critical dimension differences between high and low pattern density areas, thereby stabilizing the etching process and preventing pattern collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a hard mask scheme is applied to compensate photoresist pattern limitations, then etching precision is improved, but loading effect increases FICD in peripheral regions
Solution Approach 1:
The patent applies different hard mask widths to different regions: a first hard mask width for the memory cell region and a second hard mask width (narrower than the first) for the peripheral region. This local differentiation compensates for the loading effect in low-density peripheral regions while maintaining etching precision in high-density cell regions, thereby reducing FICD differences between regions.
2Measurement precision
If DICD of peripheral region is reduced to compensate etch CD bias, then FICD precision is improved, but photolithography process margin decreases
Solution Approach 1:
The patent implements region-specific hard mask widths that allow the peripheral region to have compensated dimensions without uniformly reducing all pattern dimensions. This localized approach improves FICD precision in peripheral regions while maintaining adequate photolithography margins by not reducing the hard mask width in the memory cell region where larger margins are needed.
3Productivity
If linewidth of semiconductor device is reduced for higher integration, then device density is improved, but gate FICD decreases making pattern formation difficult
Solution Approach 1:
The patent applies different hard mask widths to different regions to compensate for the reduced gate FICD in highly integrated devices. In the peripheral region with lower pattern density, a narrower hard mask width is used to compensate for the reduced gate dimensions, while the memory cell region maintains the original hard mask width to ensure adequate manufacturing precision despite the overall reduction in device dimensions.
Data Source
AI summary
A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer, etching the hard mask layer to form a first and a second hard mask pattern in the first and the second regions, respectively, reducing a width of the second hard mask pattern formed in the second region and etching the etch target layer using the first hard mask pattern and the second hard mask pattern having the reduced width as an etch barrier to form the etch target patterns in the first and the second regions.