Stepped Surface Formation for Multilevel Interconnect Structures
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Solution Overview
Problem
Current methods for forming multilevel metal interconnect structures in semiconductor devices face challenges in providing electrical contacts to multiple levels of conductive metal lines at low cost and with minimal processing complexity, especially in high-density 3D stacked memory structures like BiCS architecture.
Innovation Solution
A method involving the formation of a stack with alternating material layers, where trenches are created and filled with dielectric material, and then processed to form stepped surfaces with a retro-stepped dielectric structure, allowing for efficient lateral recessing and exposure of sidewalls for conductive via formation, enabling effective electrical contact across multiple levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to form multilevel metal interconnect structures, then processing complexity and cost increase, but electrical contact capability to multiple levels is achieved
Solution Approach 1:
The patent segments the interconnect structure into multiple distinct levels with stepped surfaces, where each level can be independently accessed. The conductive lines are divided into first conductive lines at a first level and second conductive lines at a second level, with dielectric material and voids separating them. This segmentation allows simplified processing for each level while maintaining electrical contact capability to multiple levels.
Solution Approach 2:
The patent introduces a vertical dimension with stepped surfaces at different heights. The first conductive lines are positioned at a first level and the second conductive lines at a second level, creating a three-dimensional interconnect structure. This dimensional arrangement enables electrical contact to multiple levels without requiring complex planar routing, reducing processing complexity while maintaining reliability.
2Productivity
If high wiring density is achieved through continuous scaling, then device capacity increases, but processing complexity and cost increase
Solution Approach 1:
The patent segments the wiring into multiple levels with first conductive lines and second conductive lines at different heights. Dielectric material and voids segment the structure vertically, allowing high wiring density to be achieved by stacking conductive lines in three dimensions rather than increasing density in a single plane. This segmentation approach maintains processing simplicity while increasing productivity.
Solution Approach 2:
The patent transitions from two-dimensional planar wiring to three-dimensional stacked wiring with conductive lines at different vertical levels. The stepped surface structure and void formation enable efficient use of vertical space, achieving high wiring density without proportionally increasing processing complexity. This dimensional change allows more wires to be packed into the same footprint area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient, cost-effective, and complex multilevel metal interconnect structures with improved electrical contact capabilities, suitable for high-density 3D memory devices like 3D NAND string memory devices.
Implementation Method 1
Portions of the dielectric material liner and portions of the second material layers are removed employing an etch process
Data Source
AI summary
A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.