Buried Guard Ring Isolation for Radiation-Hardened CMOS
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Solution Overview
Problem
The existing technologies for producing radiation-hardened integrated circuits (RHICs) are costly and inefficient, leading to a gap between commercial and military/aerospace electronics in terms of reliability and performance due to limited access to leading-edge manufacturing facilities, resulting in unreliable COTS solutions for radiation-exposed environments.
Innovation Solution
The integration of specialized structures such as buried guard rings and parasitic isolation devices into conventional CMOS fabrication processes to address radiation-induced degradation mechanisms like Total Ionizing Dose, Single Event Latch-up, and Single Event Upset, using ion-implantation and conductive layers to enhance radiation hardening without affecting baseline electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS fabrication processes are used for radiation-hardened ICs, then manufacturing cost is reduced, but radiation resistance is insufficient
Solution Approach 1:
The patent applies preliminary action by forming a heavily doped buried layer at the beginning of the fabrication process, before transistor construction. This buried layer is implanted with ions at high energy (1-3 MeV) to create a radiation-hardened foundation that prevents latch-up and reduces sensitivity to ionizing radiation throughout subsequent processing steps
Solution Approach 2:
The patent changes physical and chemical parameters by modifying the doping concentration and depth profile of the buried layer. Specifically, it uses high-energy ion implantation to achieve a peak doping concentration of 10^19 to 10^21 atoms/cm³ at a depth of 5-15 micrometers, creating optimal radiation hardening characteristics while maintaining compatibility with standard CMOS processes
2Reliability
If specialized radiation-hardened structures are added, then radiation resistance is improved, but device complexity increases
Solution Approach 1:
The patent merges the radiation-hardening function with the existing substrate structure by forming a buried layer that serves dual purposes: it acts as both a radiation-hardening element and a foundation for subsequent transistor fabrication. This integration eliminates the need for separate, complex radiation-hardening structures
Solution Approach 2:
The buried layer structure provides multiple functions simultaneously: it prevents latch-up by creating a high-conductivity path, reduces sensitivity to ionizing radiation through charge collection, and serves as a mechanical support structure. This multi-functionality reduces overall device complexity while achieving comprehensive radiation hardening
3Reliability
If high-energy ion implantation is used to form buried layer, then radiation hardening is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent uses an intermediary approach by employing a specialized ion implantation step with specific parameters (energy, dose, angle) that acts as a mediator between standard CMOS processing and radiation hardening requirements. This single well-defined process step bridges the gap without requiring multiple complex process modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides cost-effective, high-performance RHICs that significantly reduce sensitivity to ionizing radiation and latch-up failures, enabling the reuse of commercial circuit designs for radiation-hardened applications with minimal impact on circuit size or performance.
Implementation Method 1
The conductive layer is formed on the bottom surface of the substrate and configured to conduct current from the buried layer to a device package contact
Implementation Method 2
Ions are implanted into the wafer to form a substantially continuous buried layer in the wafer. The buried layer comprises a first conductivity type and a buried layer impurity concentration greater than a wafer impurity concentration
Data Source
AI summary
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.