Vertical Transistor Memory Device Area Reduction
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Solution Overview
Problem
Conventional techniques fail to effectively reduce the chip area of semiconductor memory devices using vertical transistors for DRAM memory cells and sense amplifiers, as they are not applicable to vertical transistor structures or are limited to specific types of memory cells.
Innovation Solution
A semiconductor memory device design where vertical transistors are used as select transistors in the memory cell array and also as elements of the peripheral circuit, allowing for a high-density, small-sized arrangement that reduces the overall chip area by eliminating the need for additional dummy transistors and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertical transistors are used in memory cells with embedded bit line structure, then memory cell miniaturization is achieved, but chip area reduction for peripheral circuits cannot be accomplished using conventional techniques
Solution Approach 1:
The patent applies universality by using the same vertical transistor structure for both memory cell select transistors and peripheral circuit transistors. The vertical transistor design with embedded bit line structure is made multi-functional, serving dual purposes in memory cells and peripheral circuits, thereby enabling area reduction in both regions without requiring separate design approaches.
Solution Approach 2:
The patent merges the peripheral circuit region with the memory cell array region by allowing vertical transistors to be formed in both areas using the same structure. This combining approach eliminates the need for separate peripheral circuit layouts and enables shared manufacturing processes, achieving overall chip area reduction.
2Reliability
If conventional planar MOS transistor techniques are applied to peripheral circuits, then connection reliability is improved, but applicability to vertical transistor structure is lost
Solution Approach 1:
The patent changes the structural parameters of the transistor from planar to vertical configuration while maintaining the essential functional parameters. By altering the geometric parameters (transitioning from 2D planar to 3D vertical structure), the design achieves adaptability to vertical transistor structures while preserving the functional reliability through careful design of the vertical transistor characteristics.
3Area of stationary object
If SRAM-specific transistor arrangement techniques are used, then sense amplifier area is reduced, but applicability to DRAM vertical transistor structure is eliminated
Solution Approach 1:
Instead of adapting SRAM techniques to DRAM, the patent inverts the approach by applying vertical transistor structure techniques from DRAM to the sense amplifier design. This reversal allows the sense amplifier to utilize the same vertical transistor structure as the memory cells, achieving area reduction while maintaining DRAM-specific architecture requirements.
4Stability of the object's composition
If decoupling capacitors are formed separately from memory cell capacitors, then power supply stability is ensured, but chip area is increased
Solution Approach 1:
The patent makes the memory cell capacitors multi-functional by enabling them to serve both as storage capacitors for memory operations and as decoupling capacitors for power supply stabilization. This dual-function approach eliminates the need for separate decoupling capacitor structures, achieving power supply stability while minimizing chip area.
Data Source
AI summary
A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory cell array region in a bit line extending direction; and a predetermined circuit arranged overlapping the peripheral circuit region and the memory cell array region. In the semiconductor memory device, the vertical transistors each having an upper electrode connected to the predetermined circuit are included in an end region of the memory cell array region, in which no word line is provided.