3D Memory Cell Array Interconnects With Vertical Peripheral Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of memory devices due to reduced memory cell size complicates the operation of circuits and interconnect structures, necessitating a semiconductor device with improved electrical characteristics and integration.
Innovation Solution
A semiconductor device design featuring a peripheral circuit gate structure on a substrate, a memory cell array region with vertical contacts connecting to the peripheral circuit, and an upper interconnection layer with low sheet resistance, allowing for efficient electrical connection and enhanced integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase degree of integration, then device capacity increases, but circuit and interconnect operation becomes complicated
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection structures. Bit lines and word lines are extended vertically to intersect with channel structures, enabling memory cells to be accessed through vertical contacts rather than lateral connections. This dimensional change simplifies the interconnect architecture while maintaining high integration density.
Solution Approach 2:
The memory device is divided into distinct functional regions: memory cell array regions with vertical channel structures, peripheral circuit regions for control logic, and interconnection layers positioned at different heights. This segmentation allows independent optimization of each region, reducing overall system complexity while maintaining high capacity.
2Quantity of substance
If memory cell size is reduced to increase degree of integration, then device capacity increases, but interconnection resistance increases causing response speed delays
Solution Approach 1:
Interconnection paths are extended from lateral to vertical dimensions, creating direct transmission routes between bit lines, word lines, and channel structures. This reduces the number of interconnection hops and minimizes cumulative resistance, maintaining fast response times despite reduced cell dimensions.
Solution Approach 2:
The patent combines multiple interconnection functions into integrated vertical structures that simultaneously serve as bit lines, word lines, and selection gates. This merging reduces the total interconnection length and resistance while enabling compact memory cell design with improved electrical characteristics.
Data Source
AI summary
A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.