3D Nonvolatile Memory Vertical Stacking for High Density
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Solution Overview
Problem
The integration of two-dimensional (2D) semiconductor memory devices is limited by the technology for forming fine patterns, leading to increased costs and the need for high-cost equipment, while three-dimensional (3D) semiconductor memory devices offer a solution with vertically arranged memory cells but require innovative fabrication methods to enhance integration and reduce costs.
Innovation Solution
The development of 3D nonvolatile memory devices with a substrate having a well region and a common source region, featuring a recess with a vertical stack of nonvolatile memory cells, gate electrodes, and dielectric layers, including a tunnel insulating layer, charge storage layer, barrier dielectric layer, and blocking insulating layer, optimized for high integration and reduced fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use finer patterns to increase integration, then storage density improves, but fabrication costs increase and technology reaches limitations
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking, where memory cells are arranged in multiple layers along the vertical direction. This dimensional change allows significant increase in storage density without requiring further reduction of lateral pattern dimensions, thereby avoiding the need for more expensive fine-patterning equipment and processes.
2Quantity of substance
If two-dimensional semiconductor memory devices use finer patterns to increase integration, then storage density improves, but fabrication technology reaches limitations
Solution Approach 1:
The invention moves the integration challenge from the lateral dimension to the vertical dimension by stacking memory cells in three dimensions. This approach bypasses the limitations of fine-patterning technology by not requiring smaller lateral feature sizes, thus avoiding the need for advanced lithography equipment while achieving higher storage density.
3Quantity of substance
If three-dimensional vertical stacking is implemented, then storage density improves and fabrication costs reduce, but device complexity increases
Solution Approach 1:
The fabrication process is divided into distinct stages: forming sacrificial layers and insulating layers in alternating sequence, creating openings through selective etching, depositing gate electrodes and dielectric layers, and removing sacrificial materials. This segmentation of the complex 3D fabrication process into manageable sequential steps makes the manufacturing more controllable and less complex than it would otherwise be.
Solution Approach 2:
Sacrificial layers are deposited in advance during the initial stacking process, before the final memory cell structure is complete. These preliminary sacrificial structures serve as placeholders that guide subsequent fabrication steps and are removed later to create the final vertical channel structures, simplifying the overall manufacturing sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high integration and cost-effective fabrication of 3D semiconductor memory devices with improved reliability and efficiency, minimizing current flow resistance and simplifying erasing operations, thus optimizing device performance for high-density memory applications.
Implementation Method 1
Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region
Implementation Method 2
each of the gate dielectric layers may include a composite of: (i) a tunnel insulating layer in contact with the vertical active region, (ii) a charge storage layer on the tunnel insulating layer
Implementation Method 3
the recess extends entirely through the common source region, which forms a P-N rectifying junction with the well region
Data Source
AI summary
Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.