3D Semiconductor Memory Vertical Stacking Integration Density
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the need for expensive processing equipment to form fine patterns, which restricts their high integration and increased manufacturing costs, prompting the development of three-dimensional semiconductor memory devices with vertically arranged memory cells.
Innovation Solution
A method of fabricating a three-dimensional semiconductor memory device involves forming a sacrificial pattern and source conductive layer on a substrate, creating a mold structure with insulating and sacrificial layers, forming vertical structures, and removing sacrificial layers to create a recess region, which allows for the formation of a source conductive pattern that enhances electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine patterns to increase integration, then integration density improves, but manufacturing cost increases due to expensive processing equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking, where memory cells are arranged in multiple layers along the vertical direction. This dimensional change allows integration density to increase without requiring finer lateral patterns, thereby avoiding the need for expensive lithography equipment while achieving higher capacity
2Quantity of substance
If two-dimensional semiconductor memory devices use fine patterns to increase integration, then integration density improves, but device complexity increases due to advanced processing requirements
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent achieves higher integration density using conventional two-dimensional patterning processes. This avoids the need for complex advanced lithography techniques, reducing processing complexity while maintaining high density through vertical layering of cell strings and word lines
3Quantity of substance
If three-dimensional semiconductor memory devices are fabricated with complex structures, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The three-dimensional structure stacks memory cell layers vertically using standard lithography for lateral patterning, avoiding the need for extremely precise fine-lateral-pattern formation. The vertical stacking is achieved through sequential layer deposition and etching processes that are more controllable with existing manufacturing precision capabilities
Solution Approach 2:
The memory device is segmented into multiple discrete layers including alternating word line layers and cell string layers, with each layer formed through separate deposition and etching steps. This segmentation allows each layer to be manufactured independently with standard precision, avoiding the need for highly precise monolithic pattern formation
Data Source
AI summary
Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.