3D Memory Device Vertical Stacking Reduces Chip Area
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Solution Overview
Problem
Current memory devices face challenges in achieving high element density and small size to meet increasing storage demands, as they are limited by two-dimensional structures that occupy large chip areas.
Innovation Solution
A vertically-stacked 3D memory device structure with a 3D memory array and periphery circuit, connected via a conductive structure, which reduces chip size by up to 50% by stacking these components on a single substrate, utilizing patterned metal layers and contact structures for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional memory device structure is used, then the device can be manufactured with conventional processes, but the chip area occupied by elements is large
Solution Approach 1:
The patent transitions from a two-dimensional memory device structure to a three-dimensional vertically-stacked structure. The 3D memory array is stacked above the periphery circuit on the same substrate, utilizing the vertical dimension to increase element density without expanding chip area. This dimensional change allows multiple functional blocks to coexist on a single chip with significantly reduced footprint.
2Quantity of substance
If the chip size is reduced to meet storage demands, then the storage capacity per unit area increases, but the area available for circuit elements decreases
Solution Approach 1:
By stacking the 3D memory array vertically above the periphery circuit, the patent increases storage capacity without requiring additional chip area. The vertical stacking allows the memory array to occupy the same horizontal footprint as the periphery circuit, effectively doubling the utilization of the available chip area and enabling higher storage capacity within the same or smaller footprint.
Solution Approach 2:
The 3D memory array is nested above the periphery circuit in a vertical configuration, with both structures sharing the same substrate. This nesting arrangement allows the memory array to be positioned directly over the periphery circuit, maximizing space utilization and enabling the chip to achieve higher storage capacity within a reduced area.
3Area of stationary object
If 3D vertically-stacked structure is implemented, then chip size is reduced, but the complexity of electrical connection between stacked components increases
Solution Approach 1:
The patent introduces a conductive connection structure as an intermediary element to establish electrical connections between the 3D memory array and the periphery circuit. This conductive structure acts as a mediator, simplifying the vertical interconnect architecture and managing the complexity of electrical connections between the stacked components while maintaining compact chip size.
4Quantity of substance
If more stacked planes are added to increase storage capacity, then the element density increases, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the memory device into distinct functional blocks: the periphery circuit layer and the 3D memory array layer. This segmentation allows each block to be optimized and manufactured separately using conventional processes, then integrated through conductive connections. By dividing the device into manageable segments, the manufacturing process complexity is reduced while maintaining high element density through vertical stacking.
Data Source
AI summary
A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.