3D Semiconductor Memory Device Vertical Stacking Integration
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the need for expensive equipment for fine pattern formation, which restricts their performance and cost-effectiveness, prompting the development of three-dimensional semiconductor memory devices with vertically arranged memory cells.
Innovation Solution
A semiconductor memory device with a three-dimensional structure featuring alternately stacked electrode layers and interlayer dielectric layers, a hard mask pattern with opening holes distributed in rows, and contact holes that expose pad areas, allowing for increased integration and reduced manufacturing costs through a method involving recess etching and trimming processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional semiconductor memory device is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple electrode layers and interlayer dielectric layers are stacked alternately to form a vertical structure, enabling memory cells to be arranged in the third dimension (vertical direction). This dimensional change significantly increases integration density without requiring proportionally more complex manufacturing equipment.
2Quantity of substance
If fine pattern formation technique is advanced to increase integration, then degree of integration increases, but equipment cost increases substantially
Solution Approach 1:
Instead of relying on advanced fine pattern formation techniques to increase integration, the patent uses vertical stacking to achieve higher integration density. The alternating stack of electrode layers and interlayer dielectric layers creates multiple memory cells vertically, bypassing the need for extremely fine lateral patterning and reducing dependence on expensive lithography equipment.
Solution Approach 2:
The memory device is segmented into multiple discrete layers (electrode layers and interlayer dielectric layers) that can be formed and stacked separately. This layer-by-layer segmentation allows for more manageable manufacturing processes compared to forming all patterns simultaneously, reducing the need for ultra-precise single-step patterning equipment.
3Quantity of substance
If three-dimensional structure is implemented, then integration density increases, but manufacturing process complexity increases
Solution Approach 1:
The complex three-dimensional structure is achieved through segmentation into repeating units of electrode layers and interlayer dielectric layers. Each layer can be formed using standard semiconductor fabrication techniques, and the alternating stack pattern simplifies the overall manufacturing process compared to forming complex three-dimensional structures in a single step.
Solution Approach 2:
The interlayer dielectric layers are formed preliminarily between the electrode layers during the stacking process. This preliminary formation of dielectric layers simplifies subsequent processing steps by providing a stable foundation and insulation structure before final contact hole formation and electrode patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and reduces manufacturing costs by simplifying the process, improving the operating characteristics and yield of the semiconductor memory device.
Implementation Method 1
forming a plurality of contact holes in an upper part of the stack exposed by the opening holes; increasing depths of the plurality of contact holes disposed in the row exposed by the mask pattern, by etching the stack through a recess etching process
Data Source
AI summary
A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.