3D Memory Cell Array Voltage Signal Rising Slope Control
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Solution Overview
Problem
The design and fabrication of three-dimensional (3D) memory cell arrays face challenges due to variations in driving signals, such as those provided to word lines during program, read, and erase operations, leading to reduced read margin and potential read failures due to differences in rising slopes of these signals.
Innovation Solution
A nonvolatile memory device is designed with a three-dimensional memory cell array structure where a voltage generator circuit produces first and second voltage signals with a constant rising slope, applied to selected and unselected word lines respectively, to maintain consistent driving signals across the array, preventing loss of read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If voltage signals with different rising slopes are applied to word lines in a 3D memory cell array, then the device can accommodate varying resistance across memory cell layers, but read margin is reduced and read failures occur
Solution Approach 1:
The patent applies different voltage signals with different rising slopes to different word lines based on their specific resistance characteristics. Word lines in lower memory cell layers (with higher resistance) receive voltage signals with slower rising slopes, while word lines in upper layers (with lower resistance) receive voltage signals with faster rising slopes. This local adaptation ensures uniform program speed across all word lines while maintaining adequate read margin.
Solution Approach 2:
The patent changes the rising slope parameter of voltage signals applied to word lines based on the resistance characteristics of different memory cell layers. By adjusting this electrical parameter dynamically, the system compensates for resistance variations without requiring physical structural changes, thereby maintaining both adaptability and reliability.
2Device complexity
If uniform voltage signals are applied to all word lines, then the device structure is simplified, but program speed varies across memory cell layers due to resistance differences
Solution Approach 1:
The patent implements local quality by assigning different voltage signal characteristics to different word lines based on their position in the 3D memory structure. Each memory cell layer receives customized voltage signals tailored to its resistance profile, achieving uniform program speed while accepting increased voltage signal generation complexity.
Solution Approach 2:
The patent introduces dynamic voltage signal generation where the rising slope of voltage signals is adjusted based on the specific word line being addressed. This dynamic adaptation allows the system to optimize program speed for each memory cell layer in real-time, transforming a static uniform signal approach into a flexible, performance-optimized system.
Data Source
AI summary
A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.