Solid-State Devices TRIZ Cases

Self-aligned double patterning forms buried gate electrodes and isolation patterns, improving alignment precision while reducing fabrication complexity.

Replacing indium-tin oxide with a porous zinc oxide layer reduces forward voltage and sheet resistance while enabling mass production.

An asymmetric metal mask design prevents local stress concentration and deformation, ensuring uniform light emitting layer deposition.

Segmented drive frames vibrate in opposite phases via a coupling spring, canceling common mode noise to improve angular acceleration detection precision.

Incorporating a nanocomposite layer in the electron transport part balances hole and electron transport capabilities, resolving spectroscopic redshift.

A dual gate thin film transistor structure uses auxiliary patterns to connect electrodes while maintaining physical separation between components.

A method initializes trap states in HEMT devices by applying an initialization voltage to expel trapped charges before monitoring current changes.

Segmented control circuits beneath stacked memory cell arrays reduce chip area while maintaining high-density storage capacity.

A light receiving element integrates an insulating film and metal electrode on a bias electrode to form a thin capacitor structure.

Sequentially stacked inorganic and hybrid encapsulation layers prevent impurity penetration during chamber transportation while maintaining adhesion.

A liquid crystal display array substrate uses a cross-shaped pixel electrode connected via a drain via hole to optimize the electric field distribution.

Annular housing fills through hole in carrier member to enhance bonding force, retarding moisture intrusion into chip-mounting region.

Three-stage gate structure moves photoelectrons to charge-storage sections, reducing residual electrons and mitigating manufacturing inaccuracies.

Ion implantation creates controlled defects in semiconductor layers to enhance multistable memory cell reliability and electrical parameter consistency.

Vertical stacking of common lines above gate lines increases the aperture ratio while preventing electrical short-circuits.

A pixel gate electrode partially overlaps a pixel electrode to reduce parasitic capacitance in solid-state imaging devices.

Stacking imaging and processing dies via through-silicon vias reduces die size to maintain compact dimensions in complex devices.

Isolated recesses remove wiring from the optical path to eliminate dark regions while phosphor layers redirect stray light for uniform illumination.

Dual control gates with higher-k dielectrics mitigate programming disturbances and improve charge retention in scaled trench memory structures.

Bridge lines link gate lead-out lines to reduce bezel size while maintaining uniform voltage distribution across pixel electrodes.

A semiconductor plug with protruding parts fills shallow recesses in sacrificial layers to maintain uniform lateral dimensions.

A display panel uses wavelength-correlated hole injection layer thicknesses to optimize optical paths across sub-pixels.

A crystallized indium zinc oxide film improves transparency and reduces sheet resistance in compound semiconductor light emitting devices.

An interface adjustment layer with specific resistance mitigates driving voltage increase in organic electroluminescent elements.

Inverting deposition timing before substrate thinning minimizes surface defects, boosting quantum efficiency and lowering material waste in image sensors.

Multi-primary color resist sections shield light in array substrates, reducing alignment deviations and lowering production costs.

A semiconductor diode uses a shield region to spread the depletion layer and increase junction withstand voltage.

A fluorescent light-emitting element converts triplet excitons to singlet excitons via triplet-triplet annihilation in a host-guest layer.

Forming a conductive ground structure in the substrate and bonding a top cap eliminates secondary wire bonding operations that cause defects.

Segmented thermal oxidation grows 500-micron silicon dioxide layers, reducing time and stress.

Distinct slit widths in merged pixel electrodes balance viewing angle improvements against aperture ratio loss while simplifying common voltage control.

Printing conductive ink at line intersections creates universal logic gates without cutting insulation layers.

Negative exposure mask uses peripheral reflecting surfaces to direct stray light away from pattern regions, improving dimensional accuracy.

Segmented substrate and insulating layers enable fine-pitch electrode connections, resolving line width constraints for small LED chips.

A conductive layer on the insulating substrate disperses charges to stabilize electrostatic capacitance in radiation detectors.

Deuterium substitution in the second organic layer stabilizes physical properties, lowering driving voltage while extending device lifetime.

Platinum-doped silicide layers mitigate substrate warping and junction failure from thermal expansion mismatch while lowering sheet resistivity.

Sequential silicon nitride and oxide films enable precise sidewall formation by preventing embedding in narrow gaps between gate electrodes.

Coating photoresist before deposition merges patterning steps, eliminating complex dry etching to improve device uniformity.

Sidewall contact increases interface area and reduces parasitic resistance while preventing interfacial separation during thermal processing.

A silicon carbide bidirectional transient voltage suppression device clamps overvoltages using integrated Zener diodes.

Auxiliary connection members bridge transparent and light emitting regions to reduce electrical resistance in OLED displays.

Segmenting the sensor with a pinned photodiode and triple well reduces noise, dark current, and sense node capacitance.

A backside illuminated light-receiving device uses asymmetric mesa positioning to shorten connection lines and enhance frequency characteristics.

A semiconductor integrated circuit device uses vertical power wirings below basic cells to free horizontal space for additional wirings.

An exciplex elimination layer confines charge carriers within red and green emissive layers of an organic light emitting diode.

A light emitting structure adjusts optical resonance distances to enhance color purity and brightness.

Transforming strained silicon germanium layers into relaxed regions enables epitaxial growth of distinct fin types on a single semiconductor wafer.

An asymmetric data conductor balances inclined surface areas to reduce color changes when the viewing angle is altered, preserving luminance uniformity.

Series protection device absorbs excessive gate voltage, preventing breakdown of surrounding switching devices in high side drivers.

A silicon oxynitride mask layer serves as a stop during chemical mechanical polishing with ceria-based slurries.

A sensor element integrates a ceramic hotplate carrier substrate into a plastic molded housing to provide structural support and electrical connections.

Expands via connection areas through pad rearrangement, resolving reliability drops from miniaturized component contacts.

An OLED display increases anode capacitance by overlapping expanded electrode portions with driving current lines.

A semiconductor package structure positions bonding pads away from the LED chip light-emitting surface to minimize conductive connection absorption.

Trench shielding structures reduce gate-to-drain capacitance without adding masking steps or consuming die area.

A hybrid gate electrode combines a low resistance metal inner region with a polysilicon outer region to control electron flow in power MOSFET devices.

Hybrid CMOS inverter combines indium zinc oxide and carbon nanotube thin-film transistors for efficient circuit design.

Second banks guide photoresist flow into OLED via holes, eliminating additional inkjet printing steps.

Colloidal synthesis of Ge1-xSnx alloy nanocrystals resolves polydispersity issues to achieve tunable near-infrared photoluminescence.

Unified fabrication of coupling and storage capacitors maintains precise capacitance ratios, enabling efficient data storage in multi-level cell DRAMs.

Dual cell structures ensure data unalterability while managing device complexity through merged functions.

Gray-tone-mask and plasma ashing refine TFT electrode edges, preventing isotropic shrinkage that degrades device performance.

Strategic LED chip spacing and substrate thickness balance illumination intensity with effective thermal management.

Integrated vacuum processing handles high-throughput redistribution layers while managing outgassing from molding compounds at low thermal budgets.

A mask sheet with patterned thickness variations accommodates tensile stretching forces during deposition processes.

Direct look-ahead read operations adjust sense node discharge times and word line voltages to correct threshold voltage shifts caused by adjacent cell coupling.

An inclined lateral surface on a nitride semiconductor protrusion directs light diffusion to reduce on-resistance and increase peak forward surge current.

A protection system uses segmented resistor networks to generate parallel current paths for abnormal energy discharge.

A boundary scan chain with single latches per I/O cell supports parallel operations.

Transparent electrode on substrate forms capacitance with un-doped poly-silicon, reducing photolithography masks and boosting pixel capacitance.

A parallel assisting electrode reduces cathode resistance and IR drop, preventing luminous layer damage from high-resistance ITO materials.

Vertical contacts connect word lines across stacked memory layers, eliminating extra wiring that increases chip size.

A CMOS image sensor interposer package uses a transparent substrate to route electrical signals through conductive traces.

A laminated solid-state imaging element uses a thinned substrate with an intermediate impurity region to protect the well structure.

Dual phosphors adjust emission ratios to stabilize color temperature within 100K, resolving inconsistencies from non-uniform LED chip wavelengths.

Multi-photon absorption creates gettering sinks via optical irradiation, suppressing heavy metal contamination while reducing production time and cost.

A magnetic memory device uses a nonmagnetic layer between two magnetic layers to optimize spin torque and current density.

Partition walls separate overlaid substrates into sealed regions, resolving sealing complexity while managing heat from high-power elements.

A layer transferred structure positions a trap rich layer in the handle wafer to inhibit parasitic surface conduction.

Constant rising slope voltage signals applied to selected and unselected word lines maintain stable read margin across varying layer resistances.

Sacrificial nitride layers define stepped geometry in vertical memory stacks, reducing photolithography complexity.

Relocating camera electronics to a remote control unit reduces binocular weight while maintaining image recording functionality.

Rapid thermal annealing creates small equiaxed grains in the trap-rich layer, increasing trap density to minimize parasitic surface conduction and RF losses.

Segmented bonding structures isolate adhesives from the sensing region, preventing contamination while maintaining structural integrity.

Segmented mechanical protrusions replace electrostatic forces to extract dies, resolving arcing risks while maintaining mass transfer capability.

A light-emitting element uses a cross-linked polymer layer to boost external quantum efficiency.

Removing the sacrificial layer via lift-off eliminates photo current issues and reduces photomask costs in thin-film transistor fabrication.

Back-side metal contacts eliminate front inactive areas and dissipate heat, preventing wax layer deformation under high temperature.

A low temperature oxide layer planarizes nanowire arrays and defines active regions through wet etching, reducing process steps.

A polyimide auxiliary layer between the under bump metal and bump conductive layer increases contact area and conductivity while absorbing stress.

Conductive structures connect light emitting diodes to pixel circuits through protective layers.

Vertical sidewalls in a high-k MIM capacitor reduce fabrication complexity and chip area.

A planar imaging sensor divides photo detectors into groups with staggered detection windows to capture reflected light signals.

Varying refractive index capping layers increase front brightness while minimizing color variations when viewed from the sides.

Segmented diffusion barrier patterns in a semiconductor diode suppress impurity mixing and leakage currents, improving operational reliability.

A semiconductor chip replaces failed through electrodes using transfer control signals to maintain electrical coupling between stacked devices.

Alternating sub-pixel inclination directions in adjacent rows compensates light exit angles to enhance display color uniformity.

Optimizing wire counts within apertures resolves the trade-off between enhanced polarizing performance and strict manufacturing precision requirements.

A display device partition wall uses segmented sub-layers to scatter light and prevent color mixing between pixel regions.